WILDSTAR Software Defined Radio 3U OpenVPX Module – WS3XBP-17

The WILDSTAR™ Software Defined Radio 3U OpenVPX Module (WS3XBP-17) is an assembled solution that is 100GbE-enabled, SOSA-aligned, and highly rugged and thermally-controlled. Software Defined Radio (SDR) is ideal for high-performance Cyber, EW, SIGINT, and Comms applications.

Need the same SOSA-alignment and 100GbE capability in a 6U VPX form factor? See the WILDSTAR 6XB2 6U OpenVPX Board.

These FPGA modules are SOSA-aligned Plug-In Cards (PIC). They package the WB3XBP Processor Baseboard and WWGM63 ADC/DAC Mezzanine in one 3U VPX slot. High-performance digitizing and processing are powered by three UltraScale+™ FPGAs, including a mezz-mounted Gen 3 RFSoC.

VITA 66/67 optical/RF backplane support is included.

Review other OpenVPX 3U and Xilinx FPGA boards.

General Features

  • One Virtex® UltraScale+ XCVU5P/XCVU7P FPGA
    • Up to 5520 DSP Slices and 1,724,000 logic cells
    • Up to 270 Mb of High Bandwidth, Low Latency UltraRAM
    • GTH/GTY transceivers operating up to 32.75 Gb/s
    • Two 80-bit DDR4 DRAM ports running up to 2400 MT/s
  • One Zynq® UltraScale+ MPSoC EV Motherboard Controller(XCZU7EV)
    • Quad-core 64-bit ARM® Cortex-A53 running up to 1.2GHz
    • Dual-core 32-bit Cortex-R5 real-time processor running up to 533MHz
    • 1728 DSP Slices, 504,000 logic cells and 27Mb of UltraRAM
    • Board support enabling user customization of Zynq+ design
  • One Zynq UltraScale+ RFSoC FPGA: ZU27DR, ZU28DR, or ZU47DR
    • Ultra-low latency from ADC RF input to DAC RF output
    • Firmware and Software for four channel data transmit interface and clock trigger synchronization provided in CoreFire Next™ and VHDL source
  • Multiple levels of hardware and software security
  • VITA 46.11/SOSA IPMC Support

ADC and DAC Performance

  • ADC
    • Channels: 4
    • Max Sample Rate: 5.0GSps
    • Resolution: 14 bit
  • DAC
    • Channels: 4
    • Max Sample Rate: 10.0GSps
    • Resolution: 14 bit
  • Higher channel configurations and sample rates also available

Front Panel and/or Backplane I/O

  • Eleven 50Ω SSMC or VITA 67 Mezzanine I/O
    • Four Analog Outputs
    • Four Analog Inputs
    • One Sample Clock Input
    • One Reference Clock Input
    • One Trigger Input
  • WILD FMC+ (WFMC+) next generation I/O site based on FMC+ specification
    • Accepts standard FMC and FMC+ cards (complies to FMC+ specification)
    • Allows larger form factor Annapolis cards for higher I/O density
    • Supports additional LVDS I/O for higher density ADC and DAC solutions
    • Up to 32 High Speed Serial and 100 LVDS connections to FPGA
  • Backplane optical and RF support with VITA 66/67
  • HSS connections can support protocols such as 10/40/100 Gb Ethernet and Aurora or user designed protocols – some HSS interfaces also support PCIe using FPGA hard blocks

Mechanical and Environmental

  • 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.1 spacing
  • Supports OpenVPX payload profiles such as:
    • SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n (SOSA Primary)
    • SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-n (SOSA Secondary)
  • Available with 85°C ambient air temperature or card edge support and -55°C power-on
  • Available with -65°C to 105°C storage temperature
  • Air, Air-Flow-Through or Conduction Cooled
  • Only requires +12V and +3.3VAUX from backplane
  • Developed in alignment with the SOSA™ Technical Standard
  • RT3 backplane connectors for 100G support

Clock Synchronization

  • Software-selectable external clock input or onboard PLL clock
  • All ADCs and DACs across multiple mezzanine cards can be synchronized using WILDSTAR Clock Distribution Boards and select WILDSTAR Backplanes

Application Development

  • CoreFire Next Application Design Suite
    • Full Board Support Package for Fast and Easy Application Development
    • Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
    • Develop in GUI environment or create VHDL and use HDL environment
    • Built-in Debugger for Hardware in the loop Debugging
    • Supports High-Level Synthesis (HLS) Design Flow
  • VHDL BSP packages including full synthesis and simulation support
  • Communication Cores Included (10/40Gb Ethernet and AnnapMicro Protocol cores)
  • IOPE JTAG Access through RTM or Ethernet
  • Board control and status monitoring can be local and/or remote (via Ethernet)

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Technical Documents

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