WILDSTAR 6XB2 6U OpenVPX FPGA Processor – WB6XB2

Two Xilinx® Virtex® Ultrascale+™ XCVU9P/XCVU11P/XCVU13P FPGAs with up to 29 GB of DDR4 DRAM for up to about 125 GB/s of DRAM bandwidth. Up to 8.7 million logic cells and 27,504 DSP slices per board.  Also features two WFMC+ mezzanine card with stacking support, on-board Zynq Quad ARM CPU and two FIREFLY 4x transceivers.

These FPGA boards include 2 Xilinx® Virtex® Ultrascale+™ XCVU9P/XCVU11P/XCVU13P FPGAs with 38 High Speed Serial connections performing up to 32.75 Gbps. There is one 64-bit and five 80-bit DDR4 DRAM interfaces clocked up to 1200 MHz.

If IO is required, Annapolis offers extraordinary density, bandwidth and analog conversion choices. Each card has two WILD FMC+ (WFMC+) next generation IO site based on FMC/FMC+ specification.  While accepting standard FMC and FMC+ cards (complies to FMC/FMC+ specification) it also allows larger form factor Annapolis WFMC+ cards for higher IO density.  WFMC+ also supports additional LVDS IO (100) for higher density ADC and DAC solutions as well as stacking (2 IO cards per site) when at least one card is WFMC+.  WFMC+ also brings the total available HSS up to 32 lanes for even more IO bandwidth.

There is also an on-board quad ARM CPU running up to 1.2 GHz which can be used for local application requirements.  It is accessible over backplane PCIe or Ethernet and provides dedicated AXI interfaces to all FPGAs.  It is also used to query board health like FPGA temperature and power. It is connected to the OpenVPX control plane via 1 or 10GbE.

In addition, there are 38 backplane HSS connections supporting up to 25Gb/s with new RT3 backplane connector. With included High Speed Serial (HSS) FPGA cores (including 40GBASE-KR and hardened 100GBASE-KR), there is up 182 GB/s of bandwidth on the VPX backplane which can go directly to other VPX cards, a switch or RTM, depending on backplane topology.  When using 40GBASE-KR/100GBASE-KR, there is the added reliability of Forward Error Correction (FEC) to achieve a much lower Bit Error Rate (BER).

WILDSTAR 6XB2 6U OpenVPX FPGA Processor boards are hot swappable in air cooled environments allowing for more system reliability. This feature is unique to Annapolis and was developed because our experience with OpenVPX systems has shown it invaluable so a whole chassis does not need to be shutdown to remove a single board.

There are also plenty of user backplane signals available on the Annapolis 6U Rear Transition Module (RTM) such as LVDS, FPGA HSS, IRIG, Ethernet and clocking. RTM HSS is also capable of 10Gbps signaling and can support 40GbE.

Review other OpenVPX 6U and Xilinx FPGA boards.

Two Xilinx® Virtex® Ultrascale+™ FPGAs

  • Supports XCVU9P/XCVU11P/XCVU13P FPGAs
    • Up to 24,576 DSP48E1 Slices and 7,560,000 logic cells
    • Up to 720 Mb of High Bandwidth, Low Latency UltraRAM
    • Gen4 PCIe, 150G Interlaken and 100Gb Ethernet Hard Cores
    • Four 80-bit, 5 GB DDR4 DRAM ports
    • GTH/GTY transceivers operating up to 32.75 Gb/s
    • FPGAs programmable from attached flash, JTAG or Annapolis API
    • 16nm FinFET+ process

One Xilinx® Zynq® UltraScale+™ MPSoC ZU11EG or ZU19EG Motherboard Controller

  • Processing Subsystem (PS)
    • Quad-core 64-bit ARM® Cortex-A53
    • Dual-core 32-bit Cortex-R5 real-time processor
    • Mali-400 MP2 graphics processing unit
    • One 64-bit, 4 GB DDR4 memory
    • 4 or 32 GB SLC SATA bulk storage for filesystem
    • 256Kb user SPI FRAM
  • Programmable Logic (PL)
    • Up to 2928 DSP slices or 1,143,00 logic cells
    • Up to 36Mb of High Bandwidth, Low Latency UltraRAM
    • Gen4 PCIe, 150G Interlaken and 100Gb Ethernet Hard Cores
    • One 80-bit, 5 GB DDR4 DRAM port
    • GTH/GTY transceivers operating up to 32.75 Gb/s
    • 256Kb user SPI FRAM
  • 16nm FinFET+ process
  • Provides dedicated AXI bus to IOPE FPGAs for register access
  • Board support enabling user customization of ZYNQ+ design
  • Multiple levels of hardware and software security

Backplane I/O

  • Up to 38 High Speed Serial to VPX Backplane for up to 182 GB/s
  • Two 1/10GbE and two 1GbE BASE-T to VPX Control Plane
  • 32 LVDS lines to VPX P5, 8 from each IOPE and 16 from HPE
  • 8 Single Ended 3.3V I/O to VPX Backplane P5 from HPE
  • RS-232, RS-422 or RS-485 interface to ZYNQ HPE
  • Backplane Protocol Agnostic connections support 10/40Gb Ethernet, IB capable, AnnapMicro protocol and user designed protocols
  • External clock and IRIG-B Support via Backplane
  • Radial Backplane Clock Support for OpenVPX backplane signals AUXCLK and REFCLK
    • Allows points-to-point, very high-quality backplane connections to payload cards
    • Allows a system reference clock and trigger from backplane to synchronize and clock compatible ADC/DAC mezzanine cards without front panel connections needed
    • Allows 1000s of analog channels across many backplanes/chassis to be synchronized via backplane

Front Panel I/O

  • Two Wild FMC+ (WFMC+) next generation IO sites based on FMC+ specification
    • Accepts standard FMC and FMC+ cards (complies to FMC+ specification)
    • Allows larger form factor Annapolis cards for higher IO density
    • Supports additional LVDS IO for higher density ADC and DAC solutions
    • Supports stacking (2 IO cards per site) when at least one card is WFMC+
    • Up to 32 High Speed Serial and 100 LVDS connections to FPGA
  • Simultaneous Optics and ADC/DAC use with two slots (stacked mezzanines)
  • One RF (SMA or equivalent) connection capable of input/output
  • 2 optional 4x FIREFLY Optical transceivers (optional VITA66)
  • USB UART and USB-C with USB 3.0 and DisplayPort. Both can optionally be directed to backplane

Application Development Board Support Package

  • Open Project Builder Application Design Suite
    • Full Board Support Package for Fast and Easy Application Development
    • Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
    • Develop in GUI environment or create VHDL and use HDL environment
    • Built-in Debugger for Hardware in the loop Debugging
    • Communication Cores Included (10/40Gb Ethernet, AnnapMicro Protocol)
    • VHDL Model includes Source Code for Hardware Interfaces
    • Supports High-Level Synthesis (HLS) Design Flow
  • Support for VxWorks 7 or Linux Operating Systems
  • VHDL BSP packages including full synthesis and simulation support
  • Support for Mathworks HDL Coder™ generated IP
  • IOPE JTAG Access through RTM or Ethernet
  • Board control and status monitoring can be local (stand-alone), remote (via Ethernet) or hybrid (both local and remote)

Mechanical and Environmental

  • 6U OpenVPX Compliant 1.0″ spacing
  • Available with +85°C ambient temperature support and -55°C power-on
  • Available with -65°C to +105°C storage temperature
  • Optional VITA 66/67 support
  • Integrated Heat Sink and Board Stiffener
  • Available in Industrial Temperature Grades
  • Air or Conduction Cooled
  • RTM available for additional I/O
  • Hot Swappable with air cooled variants
  • Only requires +12V and +3.3VAUX from backplane
  • Developed in alignment with the SOSA™ Technical Standard
  • RT3 backplane connectors for 100G support

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Technical Documents

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