WILDSTAR 3XBP 3U OpenVPX FPGA Processor – WB3XBP
The WILDSTAR 3XBP FPGA Processor is 100GbE-enabled, SOSA-aligned, and highly rugged and thermally-controlled. It also builds in more support and options for the data, expansion, and control planes, and includes an NVMRO option for hardware/firmware control. Watch it operate in this 100GbE SOSA-aligned Demo.
Need the same SOSA-alignment and 100GbE capability in a 6U VPX form factor? See the WILDSTAR 6XB2 6U OpenVPX Board.
These FPGA boards include 1 Virtex® UltraScale+™ XCVU5P/XCVU7P FPGA with GTH/GTY transceivers performing up to 32.75 Gbps. There are two 80-bit DDR4 DRAM interfaces clocked up to 1200 MHz.
If front panel and/or backplane IO is required, Annapolis offers extraordinary density, bandwidth and analog conversion choices. Each card has one WILD FMC+ (WFMC+) next generation IO site based on FMC/FMC+ specification. While accepting standard FMC and FMC+ cards (complies to FMC/FMC+ specification) it also allows larger form factor Annapolis WFMC+ cards for higher IO density. WFMC+ also supports additional LVDS IO (100) for higher density ADC and DAC solutions as well as stacking (2 IO cards per site) when at least one card is WFMC+. WFMC+ also brings the total available HSS up to 32 lanes for even more IO bandwidth. VITA 66/67 optical/RF backplane support is included.
There is also an on-board quad ARM CPU running up to 1.2 GHz which can be used for local application requirements. It is accessible over backplane PCIe or Ethernet and provides dedicated AXI interfaces to all FPGAs. It is also used to query board health like FPGA temperature and power. It is connected to the OpenVPX control plane via 1GbE.
The 3XBP is hot swappable, allowing for more system reliability. This feature is unique to Annapolis and was developed because our experience with OpenVPX systems has shown it invaluable so a whole chassis does not need to be shutdown to remove a single board.
- One Virtex® UltraScale+™ XCVU5P/XCVU7P FPGA
- Up to 5520 DSP Slices and 1,724,000 logic cells
- Up to 270 Mb of High Bandwidth, Low Latency UltraRAM
- GTH/GTY transceivers operating up to 32.75 Gb/s
- Two 80-bit DDR4 DRAM ports running up to 2400 MT/s
- One Xilinx® Zynq® UltraScale+™ MPSoC EV Motherboard Controller (XCZU7EV)
- Quad-core 64-bit ARM® Cortex-A53 running up to 1.2GHz
- Dual-core 32-bit Cortex-R5 real-time processor running up to 533MHz
- 1728 DSP Slices, 504,000 logic cells and 27Mb of UltraRAM
- Board support enabling user customization of ZYNQ+ design
- Multiple levels of hardware and software security
- VITA 46.11/SOSA IPMC Support
Front Panel And/Or Backplane I/O
- WILD FMC+ (WFMC+) next generation IO site based on FMC+ specification
- Accepts standard FMC and FMC+ cards (complies to FMC+ specification)
- Allows larger form factor Annapolis cards for higher IO density
- Supports additional LVDS IO for higher density ADC and DAC solutions
- Up to 32 High Speed Serial and 100 LVDS connections to FPGA
- Backplane optical and RF support with VITA 66/67
- HSS connections can support protocols such as 10/40/100 Gb Ethernet and Aurora or user designed protocols. Some HSS interfaces also support PCIe using FPGA hard blocks
Mechanical and Environmental
- 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.1 spacing
- Supports OpenVPX payload profiles such as:
- SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n (SOSA Primary)
- SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-n (SOSA Secondary)
- Available with 85C ambient air temperature or card edge support and –55C power-on
- Available with -65C to 105C storage temperature
- Air, Air-Flow-Through or Conduction Cooled
- Only requires +12V and +3.3VAUX from backplane
- Developed in alignment with the SOSA™ Technical Standard
- RT3 backplane connectors for 100G support
- Open Project Builder Application Design Suite
- Full Board Support Package for Fast and Easy Application Development
- Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
- Develop in GUI environment or create VHDL and use HDL environment
- Built-in Debugger for Hardware in the loop Debugging
- Supports High-Level Synthesis (HLS) Design Flow
- VHDL BSP packages including full synthesis and simulation support
- Communication Cores Included (10/40Gb Ethernet and AnnapMicro Protocol cores)
- IOPE JTAG Access through RTM or Ethernet
- Board control and status monitoring can be local and/or remote (via Ethernet)