Digital Beamforming

Phased Arrays and Beamforming are integral components in modern remote sensing systems. Beamforming is a signal processing technique in which signals are received and aggregated (RX) or disseminated and transmitted (TX) in such a manner that their contributions sum constructively at a desired angle, while summing destructively at other angles. This allows a system to “steer” towards a specific direction relative to the phased array face, providing significant gain relative to an omnidirectional system.

DEPLOYMENT EXAMPLE: Digital Beamforming Case Study

Early Phased Array architectures utilized beamforming electronics that were primarily analog in nature. Even as improved cost/size/weight allowed these systems to include multiple analog beamforming networks as shown in Figure 1, and therefore form multiple simultaneous beams to enable adaptive beamforming, the formation of N simultaneous beams still required the presence of N instantiations of analog combiner/beamforming networks. These analog arrays were constrained by their exact configurations and front-end electronics, lacking flexibility.

Figure 1:  Generalized Analog Beamforming Architecture

The most flexible beamforming implementation is to bring digitization as close to the antenna element as possible. This moves the beamforming processing into the digital realm, ideally into Field Programmable Gate Arrays (FPGAs), providing benefits in both density and reconfigurability. Algorithms and configurations can be swapped in via firmware updates instead of expensive hardware changes, allowing for mode changes, optimizations, and implementation of as-yet-unknown capabilities/requirements.

In such a Digital Beamformer (DBF) architecture, you would expect ADCs and DACs to be very near the elements, as shown in Figure 2. The digitized data is brought into the FPGA design space where capabilities such as waveform generators can be implemented (for TX), digital-down-converters can be implemented for RX channelization, digital-down-converters and parallel beamforming paths can be implemented, and threshold detection can be performed on constructed beams. Behind the FPGA digital space, a controller can orchestrate the overall adaptive beamforming process.

Figure 2: Generalized Digital Beamforming Architecture

An important design consideration in a Digital Beamformer is the interconnection of the digital components. For Receive beamforming, the signals from each antenna must be brought together during the beamforming process to implement the coherent summation of their parts. Such interconnects should be high-speed, high-bandwidth, and low-latency, allowing the total beamforming over all antennas to occur quickly enough that tracking can occur effectively. Common architectures for this are shown in Figure 3 and include systolic and hierarchical models.

Figure 3: Examples of Systolic (Left) and Hierarchical (Right) Beamforming Architectures

Annapolis Micro Systems Beamforming EcoSystem

Annapolis Micro Systems provides products that encompass the Digital Beamforming space via its WILD40/WILD100 EcoSystem™ for OpenVPX. This EcoSystem includes ADC and DAC Mezzanine Cards, FPGA Processing Boards, Chassis & Backplanes, Clock Distribution/Synchronization Boards, and Storage Boards.

At the front-end, Annapolis' extensive library of high-speed Analog to Digital Converters (ADCs) and Digital to Analog Converters (DACs) provide both high-density and high bandwidth due to their high channel counts and sampling rates. Increased channel count is important because it can reduce the number of digital interconnects needed in the system, as more channels can be combined in a single FPGA. Higher sample rates allow for observation of both more bandwidth and higher frequency signals, often simplifying the analog front-end needs of the system. To learn more about Annapolis WFMC+ IO card format, see this Annapolis White Paper.

These WFMC+ IO Cards mount directly to industry-leading and award-winning FPGA Processing Boards. These boards are engineered for superior performance and maximum bandwidth, providing a powerful digital computing arena for Digital Beamforming algorithms and hefty interconnect for data dissemination/aggregation.

The Annapolis WILD100 16-Slot 19″ Top-Loading Beamformer 6U OpenVPX Chassis houses the WILDSTAR boards, providing 25Gbps line rates on data and expansion planes for board-to-board communication. As shown in Figure 4 this backplane is optimized for systolic communication on the Data Plane via a Fat Pipe that traverses the length of the chassis, returning at each end of the chassis to the Clock Board in Slot 9 where High-Speed Serial FireFly Transceivers on a WILDSTAR Radial Clock Distribution Board can daisy-chain them to the next chassis in the system. This systolic path allows for direct, low-latency, FPGA-to-FPGA connections between baseboards in the chassis. This lends perfectly to a systolic beamforming implementation within a chassis, with multiple chassis being combined in a hierarchical fashion as necessary. Additional connectivity between boards is provided via Data Plane connections to a WILD OpenVPX 40 Gb Ethernet and FDR Infiniband Switch in slot 8, and via double fat pipes on the expansion plane.

Figure 4: Wild100 16-Slot 19" Top-Loading Beamformer 6U OpenVPX Chassis System Architecture

An entire Digital Beamforming system composed of multiple chassis worth of HW can be synchronized via the use of WILDSTAR Clock Distribution Module and WILDSTAR Radial Clock Distribution Boards. The WILDSTAR Clock Distribution Modules provide 12 clock and 12 trigger outputs that can be ingested by WILDSTAR Radial Clock Distribution boards, which then disseminate those signals across 12 chassis worth of backplanes to the ADCs and DACs within those Chassis. As an example of the system size facilitated by this, utilizing 12 WILDSTAR Radial Clock Distribution boards in 12 Wild100 16-Slot 19″ Top-Loading Beamformer 6U OpenVPX Chassis, with 10 WILDSTAR FPGA boards per Chassis and 2 Quad Channel ADC/DAC WFMC+ cards per WILDSTAR, a system of 960 ADC and 960 DAC channels can be fully realized with synchronization across all ADC and DAC channels. Other WILDSTAR Mezzanine Cards can provide even more channel density when considering just ADCs or DACs.

For Digital Beamforming firmware development, our patented CoreFire Next™ Design Suite, as well as our complete VHDL Board Support packages, provide all the functionality needed for fast and dependable FPGA development. When leveraging CoreFire Next, board-support cores like those shown in Figure 5 are provided for all FPGA external interfaces, implemented as simple blocks that can be dragged and dropped into your design canvas, providing the complete interface between the FPGA and the interface in question on the WILDSTAR processing board. Our VHDL includes these board-support interfaces as well, for those interested in a more traditional design environment.

Figure 5: Examples of some CoreFire Next Board Support Cores

For those interested in graphical IP-based design, CoreFire Next will speed your FPGA development process, with application services available for programs that need it. Our OpenVPX EcoSystem provides all the hardware necessary for your Digital Beamforming needs and greatly reduces your integration risk, as the interoperability of Annapolis products is guaranteed.

Annapolis can provide your solutions; contact us to start discussing how we can help solve your problems today!