Software-Defined-Radio (SDR) is a communication system in which radio components including mixers, filters, modulators/demodulators, and detection circuits are implemented in a programmable medium to provide increased flexibility and capabilities. This is shown in block diagram form below.
Figure 1: Software Defined Radio Diagram from https://upload.wikimedia.org/wikipedia/commons/2/22/SDR_et_WF.svg
An idealized SDR would include several “hard” or fixed components including an Antenna, front-end RF Hardware, and an ADC or DAC, while the rest of the functionality would be implemented in a “soft” or programmable medium. The most common “soft” device is a general purpose processor, but processors lack the I/O bandwidth and processing capabilities necessary for implementing SDRs for all but the simplest architectures.
Thankfully well architected FPGA systems can provide both the I/O bandwidth necessary and the processing capabilities needed for implementing complex SDRs, and they can do so at multi-GHz sampling rates and GHz-range bandwidths.
FPGAs are digital devices, so for a receiver the FPGA input would come from an Analog-to-Digital Converter (ADC) as shown below. A typical process would start with a mixer that rotates the signal intermediate frequency (IF) to DC, would flow through a filter-and-decimation process to reduce the bandwidth to that of interest, and might conclude with demodulation, energy detection, storage, or other processes.
Figure 2: A Typical SDR Receiver
Annapolis Micro Systems provides both the SDR hardware and firmware development tools necessary for creating SDR solutions quickly and easily. WILDSTAR™ baseboards provide FPGA processing capabilities fed directly from a large suite of I/O Mezzanine Cards, including ADCs that span from the 105MHz to 5GHz sampling rates.
For SDR development, our patented CoreFire Next™ and Open Project Builder™ Design Suites provide all the functionality needed for fast and dependable FPGA development. Board-support cores like the below ADC come as simple blocks that can be dragged and dropped into your design canvas, providing the complete interface between ADC Mezzanine Card and WILDSTAR mainboard.
Figure 3: CoreFire Next Dual 2.5GSps 10-bit ADC Core
Programmable Direct Digital Synthesis (DDS) blocks, like shown below, are provided with CoreFire Next as “macro” objects and can be used in mixing any band of the ADC to DC, with precision limited only by your adjustable phase accumulator width.
Figure 4: DDS Macro for Mixing
Filtering and downsampling can be achieved with various CoreFire Next DSP cores, some of which are shown below.
Figure 5: Some Common DSP Cores
The Channelizer implements a decimated uniform-DFT filter bank to separate incoming data into equally-spaced frequency channels, allowing the user to specify the filter coefficients and desired number of channels.
The FIR and Iterative FIR take any width of input, scalar or complex, and are user-configured to implement any number of user-specified coefficients and decimation – the Iterative FIR even implements multiple stages of filtering for you, you just need to specify the output stage you wish to propagate!
After down-conversion you can implement your required algorithm using various cores in our diverse libraries. Functionality such as QPSK demodulation is realizable in just days or a few weeks of effort, and if you need to store your data in either raw or down-converted form we have Storage capabilities to suit your needs.
The flow of a typical transmitter is largely just the reverse of a receiver, as shown below. A generated or received data stream is processed or modulated in some interesting way, the sample rate is increased via a filtering-and-interpolation process, and the signal is mixed to an intermediate frequency (IF) before being transmitted out a Digital-to-Analog Converter (DAC).
Figure 6: A Typical SDR Transmitter
Data Generation can come in many forms, but a common method is to fill a memory with synthetic data to be played back on demand. The below CoreFire Next diagrams display how easily this can be implemented via the CoreFire Next Design Suite.
Figure 7: DRAM Write Circuit for Memory Playback
The memory is filled with data from a host processor via DMA, as shown above. The host puts data in a DMA Buffer, writes an “endAddr” to the FPGA, and then data is DMAed from host to FPGA and into DRAM via the Memory Write core.
The read operation, shown below, is even simpler! The host specifies a “readEndAddr” that specifies the end value for an “address” counter that is used to request and stream the data samples out of DRAM. FPGA circuits can also easily be made to trigger these behaviors so that the host is only used at initialization, which is the common paradigm for real-time processing like this.
Figure 8: DRAM Read Circuit for Memory Playback
The entire FPGA Memory playback mechanism, including DMA, DRAM storage, and host-controlled write and read circuitry, is designed in just minutes using only 9 total cores! The circuits for Processing, Filtering, and Mixing can then be made using similar paradigms the Receiver diagram shown above.
Whatever your SDR architecture, CoreFire Next can help you achieve design success with record speed. Application design services are even available if you need a little extra help. Contact us to start discussing how we can help solve your problems today!