WILDSTAR 6XV4 6U OpenVPX FPGA Processor – WB6XV4

The WILDSTAR 6XV4 integrates one of Xilinx's new Versal™ Premium VP1702, VP1802, or VP2802 FPGAs. It is 100GbE-enabled, SOSA-aligned, and highly rugged and thermally-controlled.

Need the same Versal power and SOSA alignment and 100GbE capability in a smaller package? See the WILDSTAR 3XV1 3U OpenVPX Board.

These FPGA boards are SOSA-aligned Plug-In Cards (PIC). They include one Versal Premium VP1802/VP2802 FPGA and have eight 32-bit LPDDR4 DRAM ports running up to 3700 MT/s.

There is also an on-board dual ARM CPU running up to 1.4 GHz which can be used for local application requirements.  It is accessible over backplane PCIe or Ethernet and provides dedicated AXI interfaces to all FPGAs.  It is also used to query board health like FPGA temperature and power. It is connected to the OpenVPX control plane via 1 or 10GbE.

WILDSTAR 6XV4 6U OpenVPX FPGA Processor boards are hot swappable in air cooled environments allowing for more system reliability. This feature is unique to Annapolis and was developed because our experience with OpenVPX systems has shown it invaluable, so a whole chassis does not need to be shutdown to remove a single board.

Review other OpenVPX 6U and Xilinx FPGA boards.

 

General Features

  • One Versal™ Premium VP1802/VP2802 FPGA
    • Up to 14,352 DSP Slices and 7,352,000 logic cells
    • Up to 717 Mb of High Bandwidth, Low Latency UltraRAM
    • Eight 32-bit LPDDR4 DRAM ports running up to 3700 MT/s
    • Dual-core 64-bit ARM® Cortex-A72 running up to 1.4GHz
    • Dual-core 32-bit Cortex-R5F real-time processor running up to 600MHz
  • Multiple levels of hardware and software security
  • Supports up to 472 AI Engine Tiles and 118Mb of AI Engine Data Memory

Mechanical and Environmental

  • 6U OpenVPX (VITA 65) Compliant, 1” VITA 48.2 spacing
  • Supports OpenVPX payload profile:
    • SLT6-PAY-4F2Q1H4U1T1S1S1TU2U2T1H-10.6.4-n
  • Available with 85°C ambient air temperature or card edge support and -55°C power-on
  • Available with -65°C to 105°C storage temperature
  • Air, Air-Flow-Through or Conduction Cooled
  • Only requires +12V and +3.3VAUX from backplane
  • Developed in alignment with the SOSA™ Technical Standard 1.0
  • RT3 backplane connectors for 100G support

Application Development

  • Full Board Support Package for fast and easy Application Development
  • Includes source for all provided software components and examples on Versal PEs
  • Open CoreFire Next™ support
    • HDL generation
  • Three development flow paths:
    • Traditional RTL development flow
      • HDL/IPI -> Vivado™ -> PetaLinux project -> Bitstream
    • *NEW* Dynamic Function eXchange (DFX) RTL development flow
      • Includes abstract shell approach which avoids PetaLinux rebuilds on iterations
      • Design refactors and testing iterations significantly sped up
      • CIPs function remains active while fabric is reloaded
    • *NEW* Vitis™ Platform Project development flow

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Technical Documents

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