The WILDSTAR 3XVD integrates Xilinx's new Versal™ Premium VP1702 FPGA and is optimized for extremely low latency applications. It is 100GbE-enabled, SOSA-aligned, and highly rugged and thermally-controlled.

Pair with an LVDS-based Mezz Card (Example: WLDM30) for DRFM and other latency-sensitive applications.

Need the same Versal power and SOSA alignment and 100GbE capability in a 6U VPX form factor? See the WILDSTAR 6XV4 6U OpenVPX Board.

These SOSA-aligned Plug-In Cards (PIC) include one Versal Premium VP1702 FPGA and have two 32-bit LPDDR4 DRAM ports running up to 3700 MT/s.

The latency-optimized ADC/DAC interface offers two 12-bit ADC inputs at 3.2GSps (or one 12-bit input at 6.4GSps) and two 12-bit DAC outputs at 3.2GSps (or one 12-bit output at 6.4GSps).

There is also an on-board dual-core ARM CPU running up to 1.4 GHz which can be used for local application requirements.  It is accessible over backplane PCIe or Ethernet and provides dedicated AXI interfaces to all FPGAs.  It is also used to query board health like FPGA temperature and power. It is connected to the OpenVPX control plane via 1GbE.

The air-cooled 3XVD is hot swappable, allowing for more system reliability. This feature is unique to Annapolis and was developed because our experience with OpenVPX systems has shown it invaluable, so a whole chassis does not need to be shutdown to remove a single board.

Review other OpenVPX 3U and Xilinx FPGA boards.

General Features

  • One Versal™ Premium VP1702 FPGA
    • Up to 10,896 DSP Slices and 5,557,720 logic cells
    • Up to 541 Mb of High Bandwidth, Low Latency UltraRAM
    • Two 32-bit LPDDR4 DRAM ports running up to 3700 MT/s
    • Dual-core 64-bit ARM® Cortex-A72 running up to 1.4GHz
    • Dual-core 32-bit Cortex-R5F real-time processor running up to 600MHz
  • Optional Front panel RS422/RS485 GPIO interface
  • Optional 2/3×40/100G Optical Transceivers to VITA 66 Backplane Interface
  • Multiple levels of hardware and software security

Next Generation “WILD Mezzanine Card LVDS” (WMC-L) Site

  • Optimized for LVDS based ADC and DACs
    • For Latency Sensitive Applications
    • Annapolis Mezzanine products with “WL” prefix
  • SOSA Aligned backplane I/O
  • Optimized for VITA 66/67 interfaces
  • Optimized for cooling
  • Allows larger form factor cards for higher IO density
  • Based on FMC+
  • Available options:
    • WLDM30 TI ADC12DL3200/DAC12DL3200: 2TX (3.2 GSps)/2RX (3.2 GSps)

Mechanical and Environmental

  • 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.2 spacing
  • Supports OpenVPX payload profile:
    • SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n
    • SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-n (no P2A connectivity)
  • Available with 85°C ambient air temperature or card edge support and -55°C power-on
  • Available with -65°C to 105°C storage temperature
  • Air, Air-Flow-Through or Conduction Cooled
  • Only requires +12V and +3.3VAUX from backplane
  • Developed in alignment with the SOSA™ Technical Standard 1.0
  • RT3 backplane connectors for 100G support

Application Development

  • Full Board Support Package for fast and easy Application Development
  • Includes source for all provided software components and examples on Versal PEs
  • Open CoreFire Next™ support
    • HDL generation
  • Three development flow paths:
    • Traditional RTL development flow
      • HDL/IPI -> Vivado™ -> PetaLinux project -> Bitstream
    • *NEW* Dynamic Function eXchange (DFX) RTL development flow
      • Includes abstract shell approach which avoids PetaLinux rebuilds on iterations
      • Design refactors and testing iterations significantly sped up
      • CIPs function remains active while fabric is reloaded
    • *NEW* Vitis™ Platform Project development flow

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Technical Documents

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