WILD WLDM30 ADC & DAC LVDS
This ultra-low-latency COTS ADC and DAC Card is designed for DRFM and other latency-sensitive applications.
Compatible with any WILDSTAR mainboard with a WILD Mezzanine Card LVDS (WMC-L) Site. Example: WILDSTAR 3XVD 3U OpenVPX FPGA Processor
The WILD WLDM30 ADC & DAC LVDS is designed from the ground up for ultra-low latency from ADC SMA input to DAC SMA output. The Board Support Interface, which is available in VHDL or Open CoreFire Next Application Design Suite, allows the user to design an ultra-low latency DRFM-optimized application in minutes.
Single channel 12-bit ADC/DACs run at up to 6.4GSps each, or two channels at up to 3.2GSps each.
See all of the Annapolis Mezz Cards.
General
- Single Channel 12-bit ADC/DAC running at up to 6.4GSps each, or Two Channel at up to 3.2GSps each
- Ultra Low latency from ADC SMA input to DAC SMA output
- ADC RF to DAC RF Deterministic Latency ≤ 50ns @ 2.5GSps in Dual-Channel Mode
- Digital Bypass Mode has built-in run-time adjustable delay providing additional delay from 0ns up to 124 Sclk periods
- Up to two ADC and two DAC channels in one 3U OpenVPX slot when plugged into WILDSTAR OpenVPX FPGA mainboards
- Up to four ADC and four DAC channels in one 6U OpenVPX slot when plugged into WILDSTAR OpenVPX FPGA mainboards
- Compatible with any WILDSTAR mainboard with a WILD Mezzanine Card LVDS (WMC-L) Site
- Firmware and Software Board Support Interface provided in Open CoreFire Next and VHDL source
ADC and DAC Performance
- Channels: 1 or 2
- Sample Rate: 6.4 or 3.2GSps
- Resolution: 12 bits
I/O Connectors
- Seven 50Ω Front Panel or VITA 67 Connectors
- Two Analog ADC Inputs
- Two Analog DAC Outputs
- One External PLL Reference Input
- One High Precision Trigger Input
- One Differential External Clock Input
Mechanical and Environmental
- Integrated Heatsink and EMI / Crosstalk Shields
- Commercial and Industrial Temperatures Available
- Air Cooled and Conduction Cooled supported
Clock Synchronization
- Software-selectable external clock input or onboard PLL clock
- All ADCs and DACs across multiple mezzanine cards can be synchronized to the same sample using WILDSTAR Clock Distribution Boards
The following documentation is available for registered users of our site. Please log in or feel free to register for our site.
Technical Documents
For additional documentation, please contact your Sales Representative.