WILDSTAR 3XR2 3U OpenVPX FPGA Processor – WB3XR2

The WILDSTAR 3XR2 FPGA Processor is 100GbE-enabled, SOSA-aligned, and it leverages the processing and A/D & D/A converting power of two Gen 3 Xilinx UltraScale+™ RFSoC FPGAs. Plus, the 3XR2 offers a full-length coax-connected Analog Interface Mezzanine Site. See below for the benefits of this Site.

Need the same SOSA-alignment and 100GbE capability in a 6U VPX form factor? See the WILDSTAR 6XB2 6U OpenVPX Board.

These FPGA boards offer an Analog Interface Mezzanine Site. This site can be populated with a direct RF digitization mezz, or a 3rd party analog superheterodyne tuner to allow digitization of 18+GHz signals. An integrated tuner delivers much lower SWaP-C than a separate standalone tuner, while maintaining the ability to upgrade the tuner and digitizer/processor separately.

Populated with Gen 3 RFSoCs now, the 3XR2 is designed to accommodate the integration of Zynq RFSoC Digital Front-End (DFE) chips when they become available later in 2021.

Annapolis’ powerful BSP options include 40/100GbE IP and both VxWorks 7 and Linux support.

Review other OpenVPX 3U and Xilinx FPGA boards.

General Features

  • Supports 3rd party/customer-designed Analog Interface Cards for direct RF digitization or 18+GHz superhet tuning
  • Two Gen 3 Zynq® UltraScale+™ RFSoC FPGAs (XCZU43DR). Other configurations also available – contact factory for part number options.
    • Quad-core 64-bit ARM® Cortex-A53
    • Dual-core 32-bit ARM® Cortex-R5F
    • Up to 2.8 Mb of UltraRAM Per RFSoC
    • 8GB per RFSoC
  • VITA 46.11/SOSA IPMC Support

ADC & DAC I/O

  • ADC
    • Channels: 8
    • Sample Rate: 0.5–5.0+GSps
    • Resolution: 14 bit
  • DAC
    • Channels: 8
    • Sample Rate: 0.5–10.0+GSps
    • Resolution: 14 bit
  • Backplane RF support with VITA 67
  • HSS connections can support protocols such as 10/40/100Gb Ethernet and Aurora or user designed protocols. Some HSS interfaces also support PCIe using FPGA hard blocks

Mechanical and Environmental

  • 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.1/48.2 or 1.5” VITA 48.8 (AFT) spacing
  • Supports OpenVPX payload profiles such as:
    • SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n (SOSA Primary)
    • SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-n (SOSA Secondary)
  • Available with 85° C ambient air temperature or card edge support and -55° C power-on
  • Available with -65° C to 105° C storage temperature
  • Air, Air-Flow-Through or Conduction Cooled
  • Only requires +12V and +3.3VAUX from backplane
  • Developed in alignment with the SOSA™ Technical Standard

Application Development

  • Open Project Builder Application Design Suite
    • Full Board Support Package for Fast and Easy Application Development
    • Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
    • Develop in GUI environment or create VHDL and use HDL environment
    • Built-in Debugger for Hardware in the loop Debugging
    • Supports High-Level Synthesis (HLS) Design Flow
  • VHDL BSP packages including full synthesis and simulation support
  • Communication Cores Included (10/40Gb Ethernet and AnnapMicro Protocol cores)
  • IOPE JTAG Access through RTM or Ethernet
  • Board control and status monitoring can be local and/or remote (via Ethernet)

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Technical Documents

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