WILDSTAR 3XR2 3U OpenVPX FPGA Processor – WB3XR2
The WILDSTAR 3XR2 FPGA Processor is 100GbE-enabled, SOSA-aligned, and it leverages the processing and A/D & D/A converting power of two Gen 3 Xilinx UltraScale+™ RFSoC FPGAs. Plus, the 3XR2 offers a full-length coax-connected Analog Interface Mezzanine Site. See below for the benefits of this Site.
Need the same SOSA-alignment and 100GbE capability in a 6U VPX form factor? See the WILDSTAR 6XB2 6U OpenVPX Board.
These FPGA boards are SOSA-aligned Plug-In Cards (PIC). They offer an Analog Interface Mezzanine Site that can be populated in one of three ways:
- With a direct RF digitization mezzanine
- With simple analog circuitry (filtering, amplification, etc.)
- With a 3rd party or customer-supplied analog tuner to allow for digitization of higher frequency signals
Combining filtering and tuning with digitizing and processing delivers much lower SWaP-C than separate single-function modules, while maintaining the ability to upgrade either capability separately.
Annapolis’ powerful BSP options include 40/100GbE IP and Linux support.
Review other OpenVPX 3U and Xilinx FPGA boards.
General Features
- Supports 3rd party/customer-designed Analog Interface Cards for direct RF digitization or 18+GHz superhet tuning
- Two Gen 3 Zynq® UltraScale+ RFSoC FPGAs (XCZU43DR or XCZU48DR). Other configurations also available – contact factory for part number options.
- Quad-core 64-bit ARM® Cortex-A53
- Dual-core 32-bit ARM® Cortex-R5F
- Up to 2.8 Mb of UltraRAM Per RFSoC
- DDR4 8GB on PS, 4GB on PL per RFSoC
- VITA 46.11/SOSA IPMC Support
ADC & DAC I/O
- ADC
- Channels: Up to 8
- Sample Rate: up to 5.5GSps (maximum sample rate is RFSoC dependent)
- Resolution: 14 bit
- DAC
- Channels: Up to 8
- Sample Rate: up to 5.5GSps (maximum sample rate is RFSoC dependent)
- Resolution: 14 bit
- Backplane RF support with VITA 67
- HSS connections can support protocols such as 10/40/100Gb Ethernet and Aurora or user designed protocols. Some HSS interfaces also support PCIe using FPGA hard blocks
Mechanical and Environmental
- 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.2
- Supports OpenVPX payload profiles such as:
- SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n (SOSA Primary)
- SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-n (SOSA Secondary)
- Available up to +85°C card edge temperature and support for -55°C power-on
- Available with -65° C to 105° C storage temperature
- Air-Flow-Through or Conduction-Cooled
- Only requires +12V and +3.3VAUX from backplane
- Developed in alignment with the SOSA™ Technical Standard
Application Development
- Full Board Support Package for Fast and Easy Application Development
- Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
- Develop in GUI environment or create VHDL and use HDL environment
- Built-in Debugger for Hardware in the loop Debugging
- Supports High-Level Synthesis (HLS) Design Flow
- VHDL BSP packages including full synthesis and simulation support
- Communication Cores Included (10/40Gb Ethernet and AnnapMicro Protocol cores)
- RFPE JTAG access via cable or ethernet
- Board control and status monitoring can be local and/or remote (via Ethernet)
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Technical Documents
For additional documentation, please contact your Sales Representative.
