WILDSTAR 3XR0 3U OpenVPX FPGA Processor – WB3XR0

The air-flow-through WILDSTAR 3XR0 FPGA Processor is 100GbE-enabled and it leverages the processing and A/D & D/A converting power of two Gen 3 Xilinx UltraScale+™ RFSoC FPGAs. Plus, the 3XR0 offers a full-length coax-connected Analog Interface Mezzanine Site. See below for the benefits of this Site.

Need the same 100GbE and RFSoC capability in a SOSA-aligned board? See the WILDSTAR 3XR2 3U OpenVPX Board.

These FPGA boards offer an Analog Interface Mezzanine Site. This site can be populated with an Annapolis or 3rd party/customer-designed RF Card for front-end personalization (e.g. pre-filtering or analog conditioning) for applications of interest.

In addition to two Gen 3 Zynq UltraScale+ RFSoC FPGAs, an on-board Xilinx MPSoC provides high performing yet low power self-hosting capability thanks to the power-efficient ARM cores.

Annapolis’ powerful BSP options include 40/100GbE IP and both VxWorks 7 and Linux support.

Review other OpenVPX 3U and Xilinx FPGA boards.

General Features

  • Two Gen 3 Zynq® UltraScale+™ RFSoC FPGAs (XCZU43DR). Other configurations also available – contact factory for part number options.
    • Quad-core 64-bit ARM® Cortex-A53
    • Dual-core 32-bit ARM® Cortex-R5F
    • Up to 2.8 Mb of UltraRAM Per RFSoC
    • 8GB PS DDR4 per RFSoC
    • 4GB LP DDR4 per RFSoC
  • One Zynq® UltraScale+™ MPSoC EV Motherboard Controller (XCZU5EV)
    • Quad-core 64-bit ARM® Cortex-A53
    • Dual-core 32-bit ARM® Cortex-R5F
    • Up to 2.2 Mb of UltraRAM
      4GB of PS DDR4 DRAM
    • Board support enabling user customization of ZYNQ+ design
    • Multiple levels of hardware and software security
  • VITA 46.11/SOSA IPMC Support
  • Supports Annapolis or 3rd party/customer-designed Analog Interface Cards for front-end personalization


  • ADC
    • Channels: 4 or 8
    • Max Sample Rate: 5.0GSps
    • Resolution: 14 bit
  • DAC
    • Channels: 4 or 0
    • Max Sample Rate: 5.0GSps
    • Resolution: 14 bit
  • Backplane RF support with VITA 67
  • HSS connections can support protocols such as 10/40/100Gb Ethernet and Aurora or user designed protocols. Some HSS interfaces also support PCIe using FPGA hard blocks

Mechanical and Environmental

  • 3U OpenVPX (VITA 65) Compliant, 1.5” VITA 48.8 (AFT) spacing
  • Supports OpenVPX payload profile SLT3-PAY-2F1F2U1J-14.6.5-n
  • Available with 85° C ambient air temperature or card edge support and -55° C power-on
  • Available with -65° C to 105° C storage temperature
  • Air-Flow-Through Cooled
  • Only requires +12V and +3.3VAUX from backplane

Application Development

  • Full Board Support Package for Fast and Easy Application Development
  • Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
  • Develop in GUI environment or create VHDL and use HDL environment
  • Built-in Debugger for Hardware in the loop Debugging
  • Supports High-Level Synthesis (HLS) Design Flow
  • VHDL BSP packages including full synthesis and simulation support
  • Communication Cores Included (10/40Gb Ethernet and AnnapMicro Protocol cores)
  • RFPE JTAG access via cable or ethernet
  • Board control and status monitoring can be local and/or remote (via Ethernet)

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Technical Documents

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