WILDSTAR UltraKVP 2PE for 6U OpenVPX – WB6XU2

General Features

• One or Two Xilinx® Kintex® Ultrascale™ XCKU115 or Virtex® Ultrascale+™ XCVU5P/XCVU9P FPGAs
  • Up to 13,680 DSP Slices per board
  • Up to 5,644,000 logic cells per board
  • GTH transceivers operating up to 16.3 Gbps
  • GTY transceivers operating up to 32.75 Gbps
  • Hard 8x PCIe Gen3 endpoint for DMA and register access
  • FPGAs programmable from attached flash or Annapolis provided software API
  • 16 or 20-nm copper CMOS process
  • DDR4 DRAM ports on all FPGAs running up to 2400 MT/s
    • Two 80-bit ports per FPGA
    • Up to 20 GB/FPGA, up to 40 GB/board
    • Up to about 40 GB/s per FPGA
    • ECC optional
  • QDR-IV SRAM ports running up to 1600 MT/s (optional on IOPEs)
    • Replaces IOPE DDR4 DRAM
    • Two 72-bit ports per IOPE
    • Up to 32 MB/FPGA, up to 64 MB/board
    • Up to about 28.8 GB/s per FPGA
    • ECC optional
• Xilinx® Zynq-7000 SoC
  • Dual core ARM Cortex-A9 running up to 766 MHz
  • 1 GB DDR3 memory and 4GB eMMC bulk storage for filesystem
  • Configurable as either PCIe root complex or endpoint
  • Provides dedicated AXI bus to FPGA for register access without requiring PCIe interface
• PLX PCI Express Gen3 Switch
  • Allows expansion plane “chaining” of PCIe bus between adjacent slots. No dedicated PCIe switch slot needed.

OpenVPX Backplane I/O

• 24x High Speed Serial IO lanes to VPX Backplane (P1/P4) for 60 GB/s of Full Duplex Bandwidth
• Two PCIe Gen3 8x Connections to VPX Backplane (P2)
• 32 LVDS and 8 Single Ended lines to P3
• Backplane Protocol Agnostic connections support 10/40Gb Ethernet, IB capable, AnnapMicro protocol and user designed protocols
• External clock and IRIG-B Support via Backplane
• 10/100/1000BASE-T support for Zynq with on-board magnetics
• Radial Backplane Clock Support for OpenVPX backplane signals AUXCLK and REFCLK
  • Allows points-to-point, very high quality backplane connections to payload cards
  • Allows a system reference clock and trigger from backplane to synchronize and clock compatible ADC/DAC mezzanine cards without front panel connections needed
  • Allows 1000s of analog channels across many backplanes/chassis to be synchronized via backplane

Front Panel IO

• Two Wild FMC+ (WFMC+) next generation IO sites based on FMC+ specification
  • Accepts standard FMC and FMC+ cards (complies to FMC+ specification)
  • Allows larger form factor Annapolis cards for higher IO density
  • Supports additional LVDS IO for higher density ADC and DAC solutions
  • Supports stacking (2 IO cards per site) when at least one card is WFMC+
  • Up to 32 High Speed Serial and 100 LVDS connections to FPGA
  • Support for double wide cards
• Simultaneous Optics and ADC/DAC use with two slots
• Protocol Agnostic HSS connections support 10/40/100 Gb Ethernet, IB capable, AnnapMicro protocol and user designed protocols
• SMA for clock in, clock out or IRIG-B in supporting multiple IO standards and terminations.
• Micro USB connector for CPU serial port (uses USB to UART bridge chip)

Application Development

• Open Project Builder Application Design Suite
  • Full Board Support Package for Fast and Easy Application Development
  • Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
  • Develop in GUI environment or create VHDL and use HDL environment
  • Built-in Debugger for Hardware in the loop Debugging
  • Communication Cores Included (10/40Gb Ethernet and AnnapMicro Protocol cores)
  • VHDL Model includes Source Code for Hardware Interfaces
  • Supports High-Level Synthesis (HLS) Design Flow
• VHDL BSP packages including full synthesis and simulation support
• IOPE JTAG Access through RTM, Ethernet, or Zynq PCIe
• Board control and status monitoring can be local (stand-alone), remote (via Ethernet or PCIe) or hybrid (both local and remote)

System Management

• System Management using Intelligent Platform Management Interface (IPMI)
• Diagnostic monitoring and configuration
• Current, Voltage and Temperature Monitoring Sensors
• Hot Swappable (exclusive to WILDSTAR OpenVPX EcoSystem)

Mechanical and Environmental

• 6U OpenVPX (VITA 65) Compliant, 1” VITA 48.1 spacing
• Supports OpenVPX payload profile:MOD6-PAY-4F1Q2U2T-12.2.1-n
• Integrated Heat Sink and Board Stiffener
• Available in Extended Temperature Grades
• Air or Conduction Cooled
• RTM available for additional I/O

The following documentation is available for registered users of our site. Please log in or feel free to register for our site.

Technical Documents

• Datasheet
• Option Sheet

For additional documentation, please contact your Sales Representative.