WILDSTAR 3XB0 3U OpenVPX FPGA Processor – WB3XB0

One Virtex® UltraScale+™ XCVU9P FPGA with up to 10 GB of DDR4 DRAM for up to about 40 GB/s of DRAM bandwidth. Up to 2.8 million logic cells and 9216 DSP slices per board.  Also features WFMC+ mezzanine I/O site with stacking support, on-board Zynq Quad ARM CPU, and 1Gb Ethernet Switch.

These FPGA boards include 1 Virtex® UltraScale+™ XCVU9P FPGA with 64 High Speed Serial connections performing up to 32.75 Gbps. There are two 80-bit DDR4 DRAM interfaces clocked up to 1200 MHz.

If IO is required, Annapolis offers extraordinary density, bandwidth and analog conversion choices. Each card has one WILD FMC+ (WFMC+) next generation IO site based on FMC/FMC+ specification.  While accepting standard FMC and FMC+ cards (complies to FMC/FMC+ specification) it also allows larger form factor Annapolis WFMC+ cards for higher IO density.  WFMC+ also supports additional LVDS IO (100) for higher density ADC and DAC solutions as well as stacking (2 IO cards per site) when at least one card is WFMC+.  WFMC+ also brings the total available HSS up to 32 lanes for even more IO bandwidth.

There is also an on-board quad ARM CPU running up to 1.3 GHz which can be used for local application requirements.  It is accessible over backplane PCIe or Ethernet and provides dedicated AXI interfaces to all FPGAs.  It is also used to query board health like FPGA temperature and power. It is connected to the OpenVPX control plane via 1GbE.

In addition, there are 20 backplane HSS connections. With included High Speed Serial (HSS) FPGA cores (including 40GBASE-KR), there is up 50 GB/s of bandwidth on the VPX expansion plane which can go directly to other VPX cards, a switch or RTM, depending on backplane topology.  When using 40GBASE-KR, there is the added reliability of Forward Error Correction (FEC) to achieve a much lower Bit Error Rate (BER).

WILDSTAR™ 3XB0 3U OpenVPX FPGA Processor boards are hot swappable allowing for more system reliability. This feature is unique to Annapolis and was developed because our experience with OpenVPX systems has shown it invaluable so a whole chassis does not need to be shutdown to remove a single board.

There are also plenty of user backplane signals available on the Annapolis 6U Rear Transition Module (RTM) such as LVDS, FPGA HSS, IRIG, Ethernet and clocking. RTM HSS is also capable of 10Gbps signaling and can support multiple channels of 40GbE.

Review other OpenVPX 3U and Xilinx FPGA boards.

UltrascaleVirtex UltraScalePlus

General Features

  • One Virtex® UltraScale+™ XCVU9P FPGA
    • Up to 9216 DSP Slices and 2,835,000 logic cells
    • Up to 270 Mb of High Bandwidth, Low Latency UltraRAM
    • Up to Nine 100Gb Ethernet Hard Cores
    • GTH/GTY transceivers operating up to 32.75 Gb/s
    • Hard 4x PCIe Gen3/Gen4 endpoint for DMA and register access
    • FPGAs programmable from attached flash or Annapolis-provided software API
    • 16-nm copper CMOS process
    • DDR4 DRAM ports on all FPGAs running up to 2400 MT/s
      • Two 80-bit ports
      • 10 GB/Board
      • Up to about 40 GB/s per Board
      • ECC optional
  • One Xilinx® Zynq® UltraScale+™ MPSoC EV Motherboard Controller (XCZU7EV)
    • Quad-core 64-bit ARM® Cortex-A53 running up to 1.3GHz
    • Dual-core 32-bit Cortex-R5 real-time processor running up to 533MHz
    • Mali-400 MP2 graphics processing unit running up to 667MHz
    • H.265/H.264 Video Codec in Fabric
    • 1728 DSP Slices, 504,000 logic cells and 27Mb of UltraRAM
    • 16nm FinFET+ programmable logic
    • 4 GB 64-bit DDR4 memory running up to 1200MHz
    • 4 or 32 GB SLC SATA bulk storage for filesystem
    • Dedicated 4x PCIe Gen4 connection to IOPE, with ZYNQ+ as root complex
    • Provides dedicated AXI bus to FPGA for register access without requiring PCIe interface
    • Board support enabling user customization of ZYNQ+ design
    • Multiple levels of hardware and software security

OpenVPX Backplane I/O

  • 20 High Speed Serial IO lanes to VPX Backplane for 50 GB/s of Full Duplex Bandwidth
  • Two PCIe Gen3 capable 4x Connections to VPX Backplane, one from HPE and one from IOPE or both from IOPE
  • One 1Gb Ethernet and one 1/10Gb capable Ethernet Control Plane Connection or 2 LVDS and 2 RS-232
  • 4 LVDS lines to VPX Backplane
  • Half-size 8- or 12-contact VITA 67.3 NanoRF connector supporting 70 GHz bandwidth
  • Backplane Protocol Agnostic connections support 10/40Gb Ethernet, IB capable,
  • AnnapMicro protocol and user designed protocols
  • External clock and IRIG-B Support via Backplane
  • Radial Backplane Clock Support for OpenVPX backplane signals AUXCLK and REFCLK
    • Allows points-to-point, very high quality backplane connections to payload cards
    • Allows a system reference clock and trigger from backplane to synchronize and clock compatible ADC/DAC mezzanine cards without front panel connections needed
    • Allows 1000s of analog channels across many backplanes/chassis to be synchronized via backplane

System Management

  • System Management using Intelligent Platform Management Interface (IPMI)
  • Diagnostic monitoring and configuration
  • Current, Voltage and Temperature Monitoring Sensors
    • Hot Swappable (exclusive to WILDSTAR OpenVPX EcoSystem)

Front Panel I/O

  • WILD FMC+ (WFMC+) next generation IO site based on FMC+ specification
    • Accepts standard FMC and FMC+ cards (complies to FMC+ specification)
    • Allows larger form factor Annapolis cards for higher IO density
    • Supports additional LVDS IO for higher density ADC and DAC solutions
    • Supports stacking (2 IO cards per site) when at least one card is WFMC+
    • Up to 32 High Speed Serial and 100 LVDS connections to FPGA
  • Simultaneous Optics and ADC/DAC use with two slots
  • Protocol Agnostic HSS connections support 10/40/100 Gb Ethernet, IB capable, AnnapMicro protocol and user designed protocols
  • Micro USB connector for CPU serial port (uses USB to UART bridge chip)

Application Development

  • CoreFire Next Application Design Suite
    • Full Board Support Package for Fast and Easy Application Development
    • Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
    • Develop in GUI environment or create VHDL and use HDL environment
    • Built-in Debugger for Hardware in the loop Debugging
    • Communication Cores Included (10/40Gb Ethernet and AnnapMicro Protocol cores)
    • VHDL Model includes Source Code for Hardware Interfaces
    • Supports High-Level Synthesis (HLS) Design Flow
  • VHDL BSP packages including full synthesis and simulation support
  • IOPE JTAG Access through RTM or Ethernet
  • Board control and status monitoring can be local (stand-alone), remote (via Ethernet) or hybrid (both local and remote)

Mechanical and Environmental

  • 3U OpenVPX (VITA 65) Compliant, 1″ VITA 48.1 spacing
  • Supports OpenVPX payload profile: MOD3-PAY-2F1F2U1E-16.6.6-n
  • Available with 85C ambient air temperature or card edge support and -55C power-on
  • Available with -65C to 105C storage temperature
  • Optional VITA 66/67 support
  • Integrated Heat Sink and Board Stiffener
  • Available in Industrial Temperature Grades
  • Air or Conduction Cooled
  • RTM available for additional I/O

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