WILDSTAR 3AE1 3U OpenVPX FPGA Processor – WB3AE1

The WILDSTAR 3AE1 FPGA Processor is 100GbE-enabled, SOSA-aligned, and it leverages the processing and A/D & D/A converting power of one or two Intel Agilex Direct RF-Series AGRW014 FPGAs. Plus, the 3AE1 offers a full-length coax-connected Analog Interface Mezzanine Site. See below for the benefits of this Site.

Need the same SOSA-alignment and 100GbE capability in a 6U VPX form factor? See the WILDSTAR 6XB2 6U OpenVPX Board.

These SOSA-aligned Plug-In Cards (PIC) offer very high ADC/DAC sample rates that are integrated into the FPGAs. Each RF-Series FPGA offers four channels each of A/D and D/A converting with sample rates of 64 GS/s at 10-bit resolution.

They offer an Analog Interface Mezzanine Site that can be populated in one of three ways:

  1. With a direct RF digitization mezzanine
  2. With simple analog circuitry (filtering, amplification, etc.)
  3. With a 3rd party or customer-supplied analog tuner to allow for digitization of higher frequency signals

Combining filtering and tuning with digitizing and processing delivers much lower SWaP-C than separate single-function modules, while maintaining the ability to upgrade either capability separately.

Annapolis’ powerful BSP options include 40/100GbE IP and Linux support.

Review other OpenVPX 3U and Xilinx FPGA boards.

General Features

  • Supports Annapolis or 3rd party/customer-designed Analog Interface Cards for direct RF digitization or 18+GHz superhet tuning
  • One or two Intel Agilex Direct RF-Series AGRW014 FPGAs. (Other configurations also available – contact factory for part number options.)
  • Each FPGA provides:
    • 1,437 Logic Elements
    • 9,020 18×19 Multipliers
    • 190 Mb Embedded Memory
    • Quad Core ARM
    • 58G PAM-4, 32G NRZ XCVR
  • VITA 46.11/SOSA IPMC Support


  • ADC
    • Channels: 4
    • Sample Rate: 64GSps
    • Resolution: 10 bit
  • DAC
    • Channels: 4
    • Sample Rate: 64GSps
    • Resolution: 10 bit
  • Backplane RF support with VITA 67e
  • HSS connections can support protocols such as 10/40/100Gb Ethernet and Aurora or user designed protocols. Some HSS interfaces also support PCIe using FPGA hard blocks.

Mechanical and Environmental

  • 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.1/48.2 or 1.5” VITA 48.8 (AFT) spacing
  • Supports OpenVPX payload profiles such as:
    • SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n (SOSA Primary)
  • Available with 85° C ambient air temperature or card edge support and -55° C power-on
  • Available with -65° C to 105° C storage temperature
  • Air, Air-Flow-Through or Conduction Cooled
  • Only requires +12V and +3.3VAUX from backplane
  • Developed in alignment with the SOSA™ Technical Standard

Application Development

  • Full Board Support Package for Fast and Easy Application Development
  • VHDL flow supports High-Level Synthesis (HLS)

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Technical Documents

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