WILD100 13-Slot 3U OpenVPX Backplane – W13B20

WILD100 13-Slot 3U OpenVPX Backplane (W13B20) is a 100Gb Ethernet-enabled 3U Backplane that incorporates slots for up to eight conduction-cooled 3U VPX Payload Boards, plus two 100GbE Switches, an SBC, and two VITA 62 power supplies.

It is VITA 65 compliant, SOSA-aligned, and designed and built in USA. Its sister Chassis is WC31D0.

The 13-Slot 3U OpenVPX Backplane incorporates slots for up to eight conduction-cooled 3U VPX Payload Boards, plus two 100GbE Switches, an SBC, and two VITA 62 power supplies (Standard or 12V-Heavy).

Also available are WABGM0 Chassis Manager and WABEC0 Clock Module.

See all of the Annapolis Chassis and Backplanes.

General Features

  • Thirteen 3U OpenVPX Slots
    • Eight 14.6.11 Primary RF/Compute Intensive profile
    • One custom I/O profile in slot 1
    • Two 14.4.15 40/100GbE Switch profile
    • Two VITA 62 Power Supply Slot – Standard or 12V-Heavy
  • 25 Gbps Line Rates on Data and Expansion Planes
    • 25/40/100Gb Ethernet
    • SDR/DDR/QDR/EDR Infiniband
    • Gen 3/4 PCI Express
    • Custom protocols up to 25Gbps per lane
  • SOSA-aligned Backplane profiles
    • Payload Profile: SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n
    • Switch Profile: SLT3-SWH-6F8U-14.4.15
  • Integrated JTAG access/control from chassis manager to each slot
    • External JTAG connection with SW selectable multiplexing from each slot
    • Xilinx JTAG over ethernet via chassis manager
  • Supports VITA 66.5C and VITA 67.3C for payload slots
  • Supports standard 3U VITA 62 Supply or 12V-Heavy VITA 62 Supply
  • Integrated ultra-low skew AUXCLK/REFCLK radial distribution
    • Optionally driven by clock module WABEC0
      • Contact factory for clock generation options as well as distribution
  • Support for direct connect Front Panel IO board for ½ ATR chassis applications
  • RS-422 translation for Chassis Manager signaling to optional Front Panel IO Board
  • Support for CLK1 direct connection between payload slots (2,3,5,6,7,8,10,11) to Chassis Manager FPGA
  • Rear connectors for chassis manager, per slot JTAG, Maintenance Ports (UARTs) and control
    • Allows for optional backplane accessory interfaces without additional cabling such as WABGM0 Chassis Manager

Optional WABGM0 Chassis Manager

  • SOSA-aligned and VITA 46.11 compliant
  • Xilinx UltraScale+ ZU5EG MPSoC running Linux for CHmC
    • Processing Subsystem (PS)
      • Quad core A53 ARM running at 1.2 GHz
      • Dual core R5 ARM
      • 4GB DDR4 DRAM
      • 128MB QSPI NOR
    • Programmable Logic subsystem (PL)
      • 256K System Logic cells in Programmable Logic
      • 18Mb of UltraRAM
      • 128MB QSPI NOR
      • Dual 128KB battery backed NV SRAM
  • Integrated JTAG access/control from chassis manager to each slot
    • External JTAG connection with SW selectable multiplexing from each slot
  • Xilinx JTAG over ethernet via Chassis Manager
  • Optional MIL-STD-1553 support
  • Optional advanced security features
  • Option for Chassis Manager interfaces to be cabled directly or be routed through backplane to Front Panel IO Board

Optional WABEC0 Clock Module

  • Up to 25 Sample Clock Outputs
    • 24 singled ended Sample Clock outputs plus 1 Sample Clock test output
  • REFCLK and AUXCLK
    • 10 primary differential radial REFCLK outputs
    • 4 secondary differential radial REFCLK outputs
    • 1 REFCLK test output
    • 10 primary differential radial AUXCLK outputs
    • 4 secondary differential radial AUXCLK outputs
    • 1 AUXCLK test output

Mechanical and Environmental

  • Temperature
    • Operating: -40 to +85˚C
    • Storage: -55 to +105˚C
  • Humidity
    • Operating and Storage: 5 to 95% Noncondensing
  • Shock: 40G per VITA 47 Class OS2
  • Vibration per VITA 47 Class V3
    • 5 Hz to 100 Hz PSD increasing at 3 dB/octave
    • 100 Hz to 1000 Hz PSD = 0.1 g2/Hz
    • 1000 Hz to 2000 Hz PSD decreasing at 6 dB/octave

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Technical Documents

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