WILD Chassis Manager – WABGM0

The WILD Chassis Manager is a VITA 46.11/SOSA-aligned chassis manager that can be plugged directly into a backplane or used with an OpenVPX carrier to plug into a backplane as a payload card.

The Chassis Manager is optimized for use with VITA 65/SOSA profiles that define all payload I/O and support backplane Maintenance ports (MP01/MP02) as they provide interfaces to multiplex these and/or export over ethernet allowing for access via chassis manager ethernet connection. An optional Board Support Package (BSP) is available for custom application development and for additional feature support.

General

  • SOSA-aligned VITA 46.11 Chassis Manager
  • Xilinx UltraScale+ ZU5EG MPSoC running Linux for CHmC
    • Processing Subsystem (PS)
      • Quad core A53 ARM running at 1.2 GHz
      • Dual core R5 ARM
      • 4GB DDR4 DRAM
      • 128MB QSPI NOR
    • Programmable Logic subsystem (PL)
      • 256K System Logic cells in Programmable Logic
      • 18Mb of UltraRAM
      • 128MB QSPI NOR
      • Dual 128KB battery backed NV SRAM
  • Supports up to 16 slots for JTAG and Maintenance Port Aggregation/muxing
    • Provides 4 sets of MP01, MP01, JTAG and dedicated select lines for each for further muxing on backplane
  • Directly attaches to backplane or carrier card for slot connections
  • Has option of cabled, or backplane interface for I/O functions

Chassis Support Functions

  • Up to 8 Fan SPD/PWM interfaces
  • Up to 6 remote temperature sensing interfaces
  • Remote LEDs/Status for OverTemperature, Fan Fail and Power OK
  • SYS_Reset, NVMRO and GDISCRETE inputs

Other External Connections

  • Optional MIL-1553 interface
  • RS-232 UART for Zynq PS console (PS UART)
  • RS-232 UART for Maintenance port multiplexing (PL UART)
  • Two 10/100/1000 BASE-T interfaces from Zynq PS
  • Supports multiple battery inputs (from backplane or cable)
  • Optional 1/10Gbps rugged 850nm optical interface to Zynq PL HSS

Backplane Management Connections

  • 16 Individual maskable resets/GPIO
  • PS Inhibit/Fail for VITA 62 supplies
  • 4 Maintenance Port 1 interfaces (LVCMOS per SOSA)
  • 4 Maintenance Port 2 interfaces (LVCMOS per SOSA)
  • 4 3.3V JTAG interfaces
  • AUXCLK/REFCLK input
  • 16 GPIO (3.3V)
  • 2 10Gbps capable HSS connections to Zynq PL HSS
  • Dual IPMI connections per VITA 46.11
  • GDISCRETE, NVMRO and SYSRESET outputs

Optional Board Support Package (BSP)

  • Zynq development support
  • Enables customization of Zynq PS, PL
  • Required for some security functions

Environmental

  • Only requires 3.3V for operation
    • Designed to run from backplane 3.3VAUX
  • Includes optional on-board battery
  • Supports -65C to 105C storage temperature
  • Supports -55C partial operation
  • Supports 3U and 6U backplanes
    • Does not cover any VITA 66/67 openings allowing for full support
    • Consumes 5 slots of backplane width

 

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Technical Documents

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