WILD100 7-Slot 3U OpenVPX Backplane – W13610

The WILD100 7-Slot 3U OpenVPX Backplane (W13610) is a 100Gb Ethernet-enabled 3U Backplane that incorporates slots for up to four conduction-cooled 3U VPX Payload Boards, plus a 100GbE Switch, an SBC, and VITA 62 power supply.

It is VITA 65 compliant, SOSA-aligned, and designed and built in USA. Its sister Chassis is WC3170.

Need more capability? See the WILD100 13-Slot 3U OpenVPX Backplane (W13B20).

The 7-slot 3U Backplane incorporates slots for up to four conduction-cooled 3U VPX Payload Boards, plus a 100GbE Switch, SBC, and VITA 62 power supply, delivering up to 700W.

Also available is the secure WABGM0 Chassis Manager. It is VITA 46.11/SOSA-aligned and utilizes a Xilinx UltraScale+ ZU5EG MPSoC.

See all of the Annapolis Chassis and Backplanes.

General Features

  • Seven 3U OpenVPX Slots
    • 4 Payload Slots
    • 1 SBC Slot
    • 1 40/100GbE Switch Slot
    • 1 VITA 62 Power Supply Slot – Standard or 12V-Heavy
  • Input power is 28VDC per MIL-STD-704F
  • 25 Gbps Line Rates on Data and Expansion Planes
    • 25/40/100Gb Ethernet
    • SDR/DDR/QDR/EDR Infiniband
    • Gen 3/4 PCI Express
    • Custom protocols up to 25Gbps per lane
  • SOSA-aligned Backplane profiles
    • Payload Profile: SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n
    • Payload Profile: SLT3-PAY-1F1F2U1TU1T1U1T-14.2.16
    • Switch Profile: SLT3-SWH-6F1U7U-14.4.14
  • VITA 66.5C and VITA 67.3C for payload slots
  • Integrated ultra-low skew AUXCLK/REFCLK radial distribution
  • Chassis manager connector handles JTAG, maintenance ports (UARTs) and control

Optional WABGM0 Chassis Manager

  • SOSA-aligned and VITA 46.11 compliant
  • Xilinx UltraScale+ ZU5EG MPSoC running Linux for CHmC
    • Processing Subsystem (PS)
      • Quad core A53 ARM running at 1.2 GHz
      • Dual core R5 ARM
      • 4GB DDR4 DRAM
      • 128MB QSPI NOR
    • Programmable Logic subsystem (PL)
      • 256K System Logic cells in Programmable Logic
      • 18Mb of UltraRAM
      • 128MB QSPI NOR
      • Dual 128KB battery backed NV SRAM
  • Integrated JTAG access/control from chassis manager to each slot
    • External JTAG connection with SW selectable multiplexing from each slot
  • Xilinx JTAG over ethernet via Chassis Manager

Mechanical and Environmental

  • Temperature
    • Operating: -40 to +85°C
    • Storage: -55 to +105°C
  • Humidity
    • Operating and Storage: 5 to 95% Noncondensing
  • Shock: 40G per VITA 47 Class OS2
  • Vibration per VITA 47 Class V3
    • 5 Hz to 100 Hz PSD increasing at 3 dB/octave
    • 100 Hz to 1000 Hz PSD = 0.1 g2/Hz
    • 1000 Hz to 2000 Hz PSD decreasing at 6 dB/octave

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Technical Documents

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