5.0GSps 10-Bit ADC 12-Bit DAC WFMC+ – WWSM50

This ultra low latency 5.0GSps 10-Bit ADC 12-Bit DAC WFMC+ is specifically designed for DRFM applications with 15ns latency from SMA to SMA.

Compatible with any WILDSTAR mainboard with a WFMC+ slot.

Dual-Channel 1.5GSps 12-Bit Analog to Digital & Digital to Analog Converter Mezzanine Card

The 5.0GSps 10-Bit ADC 12-Bit DAC WFMC+ was designed from the ground up for latency sensitive DRFM applications. The Board Support Interface, which is available in VHDL or CoreFire Next Application Design Suite, was also designed from the beginning to be suited for DRFM applications. This interface provides a Digital Bypass Mode to achieve the lowest possible latency and a Fabric Space Mode to allow the user to do additional processing and manipulation of the ADC data before returning it out the DAC. The Fabric Space Mode adds only 8ns of latency. The Board Support Interface also includes a built-in Bypass Delay which can be controlled to be from 0 to 124 ADC sample clock periods. This allows the user to “walk” the latency out from the minimum Digital Bypass Mode latency to slightly beyond the Fabric Space Latency, providing for a smooth latency transition between the two modes.

The CoreFire Next Design Suite, Annapolis’ FPGA Design Tool, allows the user to design a 15ns latency DRFM-optimized application in minutes.

The 5.0GSps 10-Bit ADC 12-Bit DAC WFMC+ is shipped with a custom heatsink which enables proper cooling of the ADC. An on-board temperature monitor is also supplied which allows for real-time monitoring of the ADC’s internal die temperature.

The 5.0GSps 10-Bit ADC 12-Bit DAC WFMC+  provides high fidelity and high speed analog-to-digital and digital-to-analog conversion along with a rugged design.

See all of the Annapolis Mezz Cards.

General

  • Single Channel 10-bit ADC and 12-bit DAC running at up to 5.0GSps each
  • Ultra Low latency from ADC SMA input to DAC SMA output
  • Digital Bypass Mode (SMA-to-SMA): < 15ns (preliminary)
  • Fabric Space Mode (SMA-to-SMA): < 23ns (preliminary)
  • Digital Bypass Mode has built-in run-time adjustable delay providing additional delay from 0ns up to 124 Sclk periods
  • Capability to have two ADC channels and two DAC channels in one 6U OpenVPX slot when plugged into WILDSTAR OpenVPX FPGA cards
  • Compatible with any WILDSTAR mainboard with a WFMC+ slot
  • Firmware and Software Board Support Interface provided in CoreFire Next and VHDL source

ADC and DAC Performance

  • Sample Rate: 400 – 5000MSps
  • ADC Resolution: 10 bits
  • DAC Resolution: 12 bits

 

SMA I/O

  • One Analog Input
  • One Analog Output
  • One External PLL Reference Input
  • One High Precision Trigger Input
  • One Differential External Clock Input

Mechanical and Environmental

  • Integrated Heatsink and EMI / Crosstalk Shields
  • Commercial and Industrial Temperatures Available
  • Air Cooled and Conduction Cooled supported

Clock Synchronization

  • Software-selectable external clock input or onboard PLL clock
  • All ADCs and DACs across multiple mezzanine cards can be synchronized to the same sample using WILDSTAR Clock Distribution Boards
  • Provides capability to configure 20+ ADC and DAC channels in one COTS Annapolis 19” OpenVPX Chassis

 

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Technical Documents

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