VHDL
The VHDL Board Support is a complete design suite including all board level interfaces, simulation models and examples with host code. The examples show functionality of all board level interfaces out of the box.

The VHDL Board support for Annapolis Micro Systems, Inc. WILDSTAR™ boards is included with every board purchase, including interfaces which other vendors often do not provide free of charge such as 40 Gigabit Ethernet, XAUI and PCI Express. Simulation support for all examples is provided via Modelsim™ using board simulation models including all functional components on the board. Additionally, we provide complete support for Xilinx™ ChipScope and Intel SignalTap.
VHDL support includes:
- Synthesizable source VHDL of hardware interfaces to all FPGA accessible components (i.e. LAD Bus, DMA, DRAM, ADC, etc)
- Individual examples for each hardware interface including host source code
- Scripts for simulation, synthesis, and place & route
- Templates for user to develop VHDL-based FPGA designs
- Support for Mentor Graphics ModelSim, Xilinx ISE, Xilinx Vivado and Intel Quartus II Tools
Learn about our other FPGA programming option: CoreFire Next
WILDSTAR VHDL HW Interfaces (Full Source Code Provided)
- LAD Bus (via PCIe) for host register access
- DMA Bus over PCIe
- External Memory (SRAM, DRAM, etc.)
- HSS I/O Mezzanine Interface
- LVDS I/O Mezzanine Interface (ADC, DAC)
- Interfaces between FPGAs
- High Speed Serial I/O to Backplane
- Basic Board Functions – Clocks, Reset, LEDs
- 40 Gigabit Ethernet
- XAUI
- Infiniband
FPGA VHDL Template
- User VHDL is instantiated into the provided PE top level VHDL model
- User includes the supplied Annapolis physical interfaces
- User writes VHDL code interfacing with the Annapolis standard interfaces
Abstract Chip Level Interfaces
- Physical pad locations are available and accessible by the developer, but are abstracted within the VHDL model for ease of use
- De-multiplex multiplexed bus interfaces
- Optimized and abstracted clocking schemes
Annapolis VHDL Hardware Interface Models
- Optimized for best performance and lowest latency.
- Provide fully tested interfaces to drastically reduce customer design iterations
- Full open source, for maximum visibility and access by the developer
WILDSTAR VHDL Supported Tools
- Simulation – Mentor Graphics ModelSim
- Synthesis – ISE, Vivado, Intel Quartus II
- Place and Route – ISE, Vivado, Intel Quartus II
WILDSTAR VHDL Design Methodology
- Write VHDL user code for PE using provided template
- Connect VHDL user code to provided user interfaces (LAD bus, DMA, DRAM, etc.)
- Simulate design using included ModelSim scripts and verify its functionality against “host code” templates which simulate software API calls
- Synthesize design with ISE, Vivado, or Intel Quartus II
- Place and Route design using ISE, Vivado, Intel Quartus II
- Write C code using provided templates to program in compiled PE image and run applicable API calls
- Run the completed FPGA file on the WILDSTAR hardware and the compiled C code on the connected or remote hos
VHDL Model Simulation Environment
- Behavioral Model of all functional components on WILDSTAR
- Synthesizeable Source VHDL of hardware interfaces to all PE accessible components (LAD Bus, DMA, DRAM, mezzanine cards etc)
- Individual Source Examples for each hardware interface
- Scripts for simulation, synthesis, and place & route
- Templates for user to develop VHDL PE designs
- Complete example documentation on all of the above
- System Level Model
- Simulate the Host Computer, Place Multiple Boards in a System, and arbitrarily interconnect the Boards to each other and to External Sources
- Board Level Model
- Simulate Board Components – Memories, Buses, I/O Ports
- PE Level Model
- PE Interfaces and User Logic for driving PE pins
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For additional documentation, please contact your Sales Representative.