WILDSTAR 3XVF 3U OpenVPX FPGA Processor – WS3XVF
The WILDSTAR 3XVF integrates one AMD Xilinx Versal™ Premium VP1102 or VP1402 FPGA. It is 100GbE-enabled, SOSA-aligned, and highly rugged and thermally-controlled. It has the option for the most optical connections of our 3U Versal baseboards.
Need the same Versal power and SOSA alignment and 100GbE capability in 6U VPX? See the WILDSTAR 6XV4 6U OpenVPX Board.
These FPGA boards are SOSA-aligned Plug-In Cards (PIC). They include one Versal Premium VP1102/VP1402 FPGA, with an option for 3x100G and 4x100G optical transceivers to VITA 66 backplane interface.
There is also an on-board dual ARM CPU running up to 1.4 GHz which can be used for local application requirements. It is accessible over backplane PCIe or Ethernet and provides dedicated AXI interfaces to all FPGAs. It is also used to query board health like FPGA temperature and power. It is connected to the OpenVPX control plane via 1 or 10GbE.
WILDSTAR 3XVF 3U OpenVPX FPGA Processor boards are hot swappable in air cooled environments allowing for more system reliability. This feature is unique to Annapolis and was developed because our experience with OpenVPX systems has shown it invaluable, so a whole chassis does not need to be shutdown to remove a single board.
Review other 3U OpenVPX and Xilinx FPGA boards.
General Features
- One Versal™ Premium VP1102/VP1402 FPGA
- Up to 2,672 DSP Slices and 2,233,000 logic cells
- Up to 181 Mb of High Bandwidth, Low Latency UltraRAM
- Four 32-bit LPDDR4 DRAM ports running up to 3732 MT/s
- Dual-core 64-bit ARM Cortex-A72 running up to 1.4GHz
- Dual-core 32-bit Cortex-R5F real-time processor running up to 450MHz
- Optional 3x100G and 4x100G Optical Transceivers to VITA 66 Backplane Interface
- Multiple levels of hardware and software security
Mechanical and Environmental
- 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.2 spacing
- Supports OpenVPX payload profile:
- SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n
- SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-n (no P2A connectivity)
- Available with 85 C ambient air temperature or card edge support and -55°C power-on
- Available with -65 C to 105°C storage temperature
- Air, Air-Flow-Through or Conduction Cooled
- Only requires +12V and +3.3VAUX from backplane
- Developed in alignment with the SOSA™ Technical Standard
- RT3 backplane connectors for 100G support
Application Development
- Full Board Support Package for fast and easy Application Development
- Includes source for all provided software components and examples on Versal PEs
- Open CoreFire™ support
- HDL generation
- Three development flow paths:
- Traditional RTL development flow
- HDL/IPI -> Vivado™ -> PetaLinux project -> Bitstream
- *NEW* Dynamic Function eXchange (DFX) RTL development flow
- Includes abstract shell approach which avoids PetaLinux rebuilds on iterations
- Design refactors and testing iterations significantly sped up
- CIPs function remains active while fabric is reloaded
- *NEW* Vitis™ Platform Project development flow
- Traditional RTL development flow
The following documentation is available for registered users of our site. Please log in or feel free to register for our site.
Technical Documents
For additional documentation, please contact your Sales Representative.
