WILDSTAR UltraKVP ZP for PCIe – WBPXUW

One or two Xilinx® Kintex® Ultrascale™ XCKU115 or Virtex® Ultrascale+™ XCVU5P/XCVU9P/XCVU13P FPGAs. Up to 20 GB of DDR4 DRAM for up to 80 GB/s of DRAM bandwidth. Up to 7.5 million logic cells and 11.5 million multiplier bits per board.

These FPGA boards include two Xilinx® Kintex UltraScale or Virtex™ UltraScale FPGAs with High Speed Serial connections performing up to 25+ Gbps.  On each Compute Processing Element (CPE) FPGA there are two 32-bit and 72-bit DDR4 DRAM interfaces clocked up to 1200 MHz.

There is also an on-board dual ARM CPU running up to 766 MHz which can be used for local application requirements without using PCIe bandwidth.  It accessible over PCIe and also had dedicated AXI interfaces to all FPGAs.  There is an RJ45 Ethernet port and UART for ease of application development.  The on-board CPU can also utilize the PCIe bus back to host CPU for Ethernet and control.

PCIe boards connect to the host system via a Gen 3 PCI Express switch which provides a x16 interface to the host (up to 16 GB/s) and x8 Gen3 interfaces to each FPGA (up to 8 GB/s). There is also plenty of on-board inter-FPGA HSS connections for data movement.

To ensure safe and reliable processing, WILDSTAR UltraKVP ZP for PCIe boards come equipped with a proactive thermal management system. Sensors across the board monitor power and temperature, with automatic shutdown capability to prevent excessive heat buildup. WILDSTAR UltraK for PCIe boards are built with a rugged, durable design.

Review other PCIe FPGA boards or other Xilinx FPGA boards.

Ultrascale

General Features

  • One or Two Xilinx® Kintex® Ultrascale™ XCKU115 or Virtex® Ultrascale+™ XCVU5P/XCVU9P/XCVU13P FPGAs
    • Up to 24,576 DSP Slices per board
    • Up to 7,560,000 logic cells per board
    • GTH transceivers operating up to 16.3 Gbps
    • GTY transceivers operating up to 32.75 Gbps
    • Hard 8x PCIe Gen3 endpoint for DMA and register access
    • FPGAs programmable from attached flash or Annapolis provided software API
    • 16 or 20-nm copper CMOS process
  • IOPE DDR4 DRAM ports on all FPGAs running up to 2400 MT/s
    • Two 80-bit ports per FPGA
    • Up to 20 GB/FPGA, up to 60 GB/board
    • Up to about 40 GB/s per FPGA
    • ECC optional
  • Xilinx® Zynq® UltraScale+™ MPSoC EG Motherboard Controller (XCZU3EG)
    • Quad-core 64-bit ARM® Cortex-A53 running up to 1.3GHz
    • Dual-core 32-bit Cortex-R5 real-time processor running up to 533 MHz
    • Mali-400 MP2 graphics processing unit running up to 600 MHz
    • 16nm FinFET+ programmable logic
    • 2 GB 32-bit DDR4 memory running up to 1200 MHz
    • 4 GB SLC eMMC bulk storage for filesystem
    • Dedicated 4x PCIe Gen2 connection to IOPE, with Zynq® UltraScale+™ MPSoC as endpoint
    • Provides dedicated AXI bus to FPGA for register access without requiring PCIe interface
    • Board support enabling user customization of Zynq® UltraScale+™ MPSoC design
    • Multiple levels of hardware and software security
  • PLX PCI Express Gen3 Switch
    • Allows 16x Gen3 link to motherboard to support full bandwidth 8x Gen3 from each FPGA

Front Panel I/O

  • One Wild FMC+ (WFMC+) next generation IO site based on FMC+ specification
    • Accepts standard FMC and FMC+ cards (complies to FMC+ specification)
    • Allows larger form factor Annapolis cards for higher IO density
    • Supports additional LVDS IO for higher density ADC and DAC solutions
    • Supports stacking (2 IO cards per site) when at least one card is WFMC+
    • Up to 32 High Speed Serial and 100 LVDS connections to FPGA
    • Support for double wide cards
  • Simultaneous Optics and ADC/DAC use with two slots
  • Protocol Agnostic HSS connections support 10/40/100 Gb Ethernet, IB capable, AnnapMicro protocol and user designed protocols
  • RF connector for clock in, clock out or IRIG-B supports multiple IO standards and terminations
  • Micro USB connector for CPU serial port (uses USB to UART bridge chip)

Application Development

  • Project Builder Application Design Suite
    • Full Board Support Package for Fast and Easy Application Development
    • Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
    • Develop in GUI environment or create VHDL and use HDL environment
    • Built-in Debugger for Hardware in the loop Debugging
    • Communication Cores Included (10/40Gb Ethernet and AnnapMicro Protocol cores)
    • VHDL Model includes Source Code for Hardware Interfaces
    • Supports High-Level Synthesis (HLS) Design Flow
  • VHDL BSP packages including full synthesis and simulation support
  • FPGA JTAG Access through standard Xilinx JTAG Connector or Ethernet
  • Board control and status monitoring can be local (stand-alone), remote (via Ethernet) or hybrid (both local and remote)

System Management

  • System Management using Intelligent Platform Management Interface (IPMI)
  • Diagnostic monitoring and configuration
  • Current, Voltage and Temperature Monitoring Sensors
  • Drivers and APIs for Host Systems running Windows and Linux are included

Mechanical and Environmental

  • 10.5” length for wider chassis compatibility
  • Does not require a “Full Length” slot
  • Integrated Heat Sink and Board Stiffener
  • External +12V Power Connector

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Technical Documents

For additional documentation, please contact your Sales Representative.

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