WILDSTAR A5 for 6U OpenVPX
Up to three Altera Stratix® V FPGAs per board with choice of GX parts up to 5SGXAB or GS parts up to 5SGSD8, up to 96 MB of QDRII+ SRAM for 59 GB/s of SRAM bandwidth and up to 8 GB of DDR3 DRAM for 51.2 GB/s of DRAM bandwidth. Up to 2.8 million logic elements and 4.3 million multiplier bits per board. Air Cooled Only.
These FPGA boards include 3 Altera Stratix V FPGAs with 48 High Speed Serial connections performing up to 14.1 Gbps. On each Compute Processing Element (CPE) FPGA there is six 72-bit QDRII+ SRAM interfaces clocked up to 550 MHz. The IO Processing Element (IOPE) FPGA has four 32-bit DDR3 DRAM ports clocked at up to 800 MHz.
With included High Speed Serial (HSS) FPGA cores (including 40GBASE-KR), there is up 20 GB/s of bandwidth on the VPX data plane which can go directly to other VPX cards or to a switch, depending on backplane topology. In addition, there is 16 GB/s of PCI Express Gen 3 bandwidth on the VPX Expansion Plane with an 8x Gen3 connection to each FPGA through a non-blocking PCIe switch. When using 40GBASE-KR, there is the added reliability of Forward Error Correction (FEC) to achieve a much lower Bit Error Rate (BER).
If IO is required, Annapolis offers extraordinary density, bandwidth and analog conversion choices. Each 6U card has 2 mezzanine IO sites which can support up to 4 WILDSTAR™ Mezzanine cards as well as a QSFP+ option (on WS7 and WS A5 board) that allows for 6 QSFP+ transceivers per slot. These options can be mix and matched to meet customer needs. Some configurations utilize a second slot (for example the QSFP+ option and WILDSTAR Mezzanine card used in a single IO Site).
WILDSTAR A5 and V7 FPGA boards are hot swappable allowing for more system reliability. This feature is unique to Annapolis and was developed because our experience with OpenVPX systems has shown it invaluable so a whole chassis does not need to be shutdown to remove a single board.
Annapolis OpenVPX FPGA cards include an on-board dual core 1.2 GHz PowerPC. This also has a connection to PCIe infrastructure (which includes FPGAs) and can be used by customers for application requirements. It is also used query board health like FPGA temperature and power. It is connected to the OpenVPX control plane via 1GbE.
There are also plenty of user backplane signals available on the Annapolis 6U Rear Transition Module (RTM) such as LVDS, FPGA HSS, IRIG, Ethernet and clocking. RTM HSS is also capable of 10Gbps signalling and supports multiple channels of 40GbE.
One, Two or Three ALTERA STRATIX® V FPGAS
- Up to three Altera Stratix® V FPGA Processing Elements: 5SGSD6, 5SGSD8, 5SGXA7, 5SGXA9, 5SGXAB
- Up to 8 GB of DDR3 DRAM for 51.2 GB/s of DRAM bandwidth
- Up to 96 MB of QDRII+ SRAM for 48 GB/s of SRAM bandwidth
- PCIe Gen3 8x from each FPGA to on-board PCIe switch
- 16x High Speed Serial IO lanes to VPX Data Plane (P1) for 20 GB/s of Full Duplex Bandwidth
- Up to 16x High Speed Serial FPGA connections to P5
- 8x High Speed Serial IO lanes to P4
- Two PCIe Gen3 8x Connections to VPX Expansion Plane (P2)
- 32 LVDS and 8 Single Ended lines to P3
- Backplane Protocol Agnostic connections support 10/40Gb Ethernet, SDR/DDR/QDR Infiniband, AnnapMicro protocol and user designed protocols
Front Panel I/O
- Accepts Standard Annapolis WILDSTAR Mezzanine Cards, including a wide variety of WILDSTAR ADC and DAC Mezzanine Cards
- Three or six optional built-in Front Panel QSFP+ Transceivers running at up to 56.4 Gbps each for 42.3 GB/s of Full Duplex Bandwidth
- 1 Gb Ethernet RJ45 connector for Remote Host Access
- External clock and IRIG-B Support via Front Panel SMA
- QSFP+ Protocol Agnostic connections support 10/40Gb Ethernet, SDR/ DDR/QDR Infiniband, AnnapMicro protocol and user-designed protocols
Dual Core Processor APM86290
- Host Software: Linux API and Device Drivers
- Each core runs up to 1.2 GHz
- 2 GB of DDR3 DRAM
- 4GB SATA SSD and 16MB NOR Boot Flash
- 4x PCIe Gen2 connection to on-board PCIe Switch
- Full CoreFire NextTM Board Support Package for Fast and Easy Application Development
- 10/40Gb Ethernet and AnnapMicro Protocol Cores Included
- Open VHDL Model including Source Code for Hardware Interfaces
- Open VHDL IP Package for Communication Interfaces
- SignalTap Access through RTM
- System Management using Intelligent Platform Management Interface (IPMI)
- Diagnostic monitoring and configuration
- Current, Voltage and Temperature Monitoring Sensors
- Hot Swappable (exclusive to WILDSTAR OpenVPX EcoSystem)
Mechanical and Environmental
- 6U OpenVPX (VITA 65) Compliant, 1” VITA 48.1 spacing
- Supports OpenVPX payload profile:MOD6-PAY-4F1Q2U2T-12.2.1-n
- Integrated Heat Sink and Board Stiffener
- Available in Extended Temperature Grades
- Air Cooled with Conduction Cooled path
- RTM available for additional I/O
Up to three Xilinx Virtex 7 FPGAs per board with VX690T or VX980T FPGAs, up to 8 GB of DDR3 DRAM for 51.2 GB/s of DRAM bandwidth and up to 128 MB of QDRII+ SRAM for 64 GB/s of SRAM bandwidth. Up to 2.9 million logic cells and 4.9 million multiplier bits per board. Air […]