One VX690T or VX980T Virtex 7 FPGA per board with up to 2 GB of DDR3 DRAM for 12.8 GB/s of DRAM bandwidth and up to 32 MB of QDRII+ SRAM for 8 GB/s of SRAM bandwidth. Up to 1 million logic cells and 1.6 million multiplier bits per board. Air Cooled Only.

Xilinx Virtex 7 OpenVPX 3U FPGA Processing Board

These FPGA boards include 1 Xilinx Virtex 7 FPGA with 64 High Speed Serial connections performing up to 13.1 Gbps. There is two 36-bit QDRII+ SRAM interfaces clocked up to 500 MHz and two 32-bit DDR3 DRAM ports clocked at up to 800 MHz.

With included High Speed Serial (HSS) FPGA cores (including 40GBASE-KR), there is up 10 GB/s of bandwidth on the VPX data plane which can go directly to other VPX cards or to a switch, depending on backplane topology. In addition, there is up to 20 GB/s of bandwidth on the VPX Expansion Place. When using 40GBASE-KR, there is the added reliability of Forward Error Correction (FEC) to achieve a much lower Bit Error Rate (BER).

If IO is required, Annapolis offers extraordinary density, bandwidth and analog conversion choices. Each 3U card has 1 mezzanine IO sites which can support up to 2 WILDSTAR™ Mezzanine cards as well as a QSFP+ option (on WS7 and WS A5 board) that allows for 3 QSFP+ transceivers per slot. These options can be mix and matched to meet customer needs. Some configurations utilize a second slot (for example the QSFP+ option and WILDSTAR Mezzanine card used in a single IO Site).

WILDSTAR A5 and V7 FPGA boards are hot swappable allowing for more system reliability. This feature is unique to Annapolis and was developed because our experience with OpenVPX systems has shown it invaluable so a whole chassis does not need to be shutdown to remove a single board.

Annapolis OpenVPX FPGA cards include an on-board dual core 1.2 GHz PowerPC with direct FPGA 4x PCIe connection which can be used by customers for application requirements. It is also used query board health like FPGA temperature and power. It is connected to the OpenVPX control plane via 1GbE.

There are also plenty of user backplane signals available on the Annapolis 6U Rear Transition Module (RTM) such as LVDS, FPGA HSS, IRIG, Ethernet and clocking. RTM HSS is also capable of 10Gbps signalling and supports multiple channels of 40GbE.

Review other OpenVPX 3U and Xilinx FPGA boards.


General Features

  • One Xilinx Virtex 7 VX690T or VX980T FPGA
  • Up to 2 GB of DDR3 DRAM for 12.8 GB/s of DRAM bandwidth
  • Up to 32 MB of QDRII+ SRAM for 8 GB/s of SRAM bandwidth

Backplane I/O

  • 24x High Speed Serial IO lanes to VPX Backplane (P1/P2) for 30 GB/s of Full Duplex Bandwidth
  • Two PCIe Gen3 8x Connections to VPX Backplane (P1)
  • Eight LVDS lines to P2
  • Backplane Protocol Agnostic connections support 10/40Gb Ethernet, SDR/DDR/QDR Infiniband, AnnapMicro protocol and user designed protocols
  • External clock and IRIG-B Support via Backplane
  • Radial Backplane Clock Support for OpenVPX backplane signals AUXCLK and REFCLK
    • Allows points-to-point, very high quality backplane connections to payload cards
    • Allows 10MHz clock and trigger from backplane to synchronize and clock compatible ADC/DAC mezzanine cards without front panel connections needed
    • Allows 1000s of analog channels across many backplanes/chassis to be synchronized via backplane

Front Panel I/O

  • Accepts Standard Annapolis WILDSTAR Mezzanine Cards, including a wide variety of WILDSTAR ADC and DAC Mezzanine Cards
  • Three optional built-in Front Panel QSFP+ Transceivers running at up to 52.4 Gbps each for 39 GB/s of Full Duplex Bandwidth
  • Simultaneous QSFP and Mezzanine Card use
  • QSFP+ Protocol Agnostic connections support 10/40Gb Ethernet, SDR/DDR/QDR Infiniband, AnnapMicro protocol and userdesigned protocols

Dual Core Processor APM86290

  • Host Software: Linux API and Device Drivers
  • Each core runs up to 1.2 GHz
  • 2 GB of DDR3 DRAM
  • 4 GB SATA SSD and 16MB NOR Boot Flash
  • 4x PCIe Gen2 connection to Virtex 7 FPGA

Application Development

  • Full CoreFire NextTM Board Support Package for Fast and Easy Application Development
  • 10/40Gb Ethernet and AnnapMicro Protocol Cores Included
  • Open VHDL Model including Source Code for Hardware Interfaces
  • Open VHDL IP Package for Communication Interfaces
  • Chipscope Access through RTM

System Management

  • System Management using Intelligent Platform Management Interface (IPMI)
  • Diagnostic monitoring and configuration
  • Current, Voltage and Temperature Monitoring Sensors
  • Hot Swappable (exclusive to WILDSTAR OpenVPX EcoSystem)

Mechanical and Environmental

  • 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.1 spacing
  • Supports OpenVPX payload profile:MOD3-PAY-2F4F2U-16.2.10-n
  • Integrated Heat Sink and Board Stiffener
  • Available in Extended Temperature Grades
  • Air Cooled with Conduction Cooled path
  • RTM available for additional I/O

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