WILDSTAR 3U OpenVPX Clock Board – WP3C21

The WILDSTAR 3U OpenVPX SOSA™-Aligned Clock Distribution Board is designed to generate and distribute the high-performance clocks needed to meet stringent RF clocking requirements. The WP3C21 clock card supports flexible input and output clock configurations to support a wide range of use cases.

The WP3C21 can distribute or generate up to 12GHz clocks. Clocks can be generated from an ultra-low phase noise fixed frequency PLL or from an adjustable PLL synthesizer. It can distribute 11 copies of AUXCLK and REFCLK across the backplane, as well as up to 11 RF copies across coax though the VITA 67 backplane interface. It includes an on-board Xilinx UltraScale+™ Zynq® to configure the card on power up for true stand alone functionality as well as update and/or change the configuration in-system.

General Features

  • Provides Capability to Synchronize up to 11 ADC/DAC WFMC+ per Clock Distribution Board
  • 11 Differential Radial REFCLK Outputs
  • 11 Differential Radial AUXCLK Outputs
  • 11 Single-Ended VITA 67 Clock RF Connections
  • Front Panel LEDs for Board Status
  • Supports Clock Frequencies Up to 12GHz
  • AUXCLK Outputs are Synchronized to REFCLK
  • Ultra-Low Phase Noise Distribution
  • Developed in alignment with SOSA 1.0 Technical Standard

Selectable Clock And Trigger Sources

  • Dynamically Selectable Clock Source
    • External RF Connection
    • Variable Frequency PLL Synthesizer
    • Fixed Frequency PLL
  • Dynamically Selectable Reference Clock Source
    • External RF Connection
    • Fixed Frequency Oscillator
    • REFCLK (from VPX Backplane Bussed Connection)
    • Optional Ultra-Low Phase Noise OCXO
  • Dynamically Selectable Trigger Source
    • External RF Connection
    • AUXCLK (from VPX Backplane Bussed Connection)
    • Front Panel Push Button
    • Software Initiated Trigger

System Management

  • Flexible Board Control
    • Backplane IPMI Calls
    • Front panel or backplane (SOSA) UART interface
    • Backplane ethernet interface
  • System Management (VITA 46.11) compatible Xilinx Zynq UltraScale+ MPSoC (XCZU5EV)
  • On-Board current, voltage, and temperature monitoring sensors
  • Diagnostic monitoring and configuration
  • High Output swing: +10 dBm nominal output up to 12GHz

Mechanical And Environmental

  • 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.1 and 48.2 spacing
  • Supports OpenVPX payload profiles:
    • SLT3x-TIM-2S1U22S1U2U1H-14.9.2-n (Full support)
    • SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n (Limited support – consult factory)
  • Integrated EMI/Crosstalk Shield and Board Stiffener
  • Commercial and Industrial Temperatures Available
  • Air, Air Flow Through and Conduction-Cooled methods supported
  • Optionally Hot Swappable

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Technical Documents

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