WILD100 OpenVPX Quick-Turn Chassis Family – WCG000

WCG000 is a family of quick-turn air-cooled 3U and 6U OpenVPX Chassis with conduction-cooled slots for lab use. They are 100Gb Ethernet-enabled and SOSA™-aligned, and include a Chassis and Backplane. Quick-turn Chassis frames support all WILD100 Backplanes. A Chassis Manager is also available.

Compatible WILD100 FPGA Digitizing/Processing Boards, Switch, Storage, SBC, VITA blocks and cables are also available.

It is VITA 66.5C and VITA 67.3C capable, SOSA-aligned, and designed and built in USA.

This family of front-loading, air-cooled 3U and 6U VPX Chassis features up to 16 conduction-cooled slots. Accompanying short-lead-time 100GbE WILD100 Backplanes utilize SOSA-aligned payload and switch profiles.

An optional Chassis Manager is SOSA-aligned and VITA 46.11 compliant.

See all of the Annapolis Chassis and Backplanes.

Chassis and Backplane

  • SOSA-aligned
  • Front-loading, air-cooled 3U or 6U OpenVPX Chassis with up to 16 conduction-cooled slots
  • Available with standard or special WILD100 Backplanes, with up to 16 payload, switch, and power supply slots
  • Input power is 28VDC per MIL-STD-704F
  • 25 Gbps Line Rates on Data and Expansion Planes
    • 25/40/100Gb Ethernet
    • SDR/DDR/QDR/EDR Infiniband
    • Gen 3/4 PCI Express
    • Custom protocols up to 25Gbps per lane
  • SOSA-aligned Backplane profiles available
    • Payload Profile: SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n
    • Payload Profile: SLT3-PAY-1F1F2U1TU1T1U1T-14.2.16
    • Switch Profile: SLT3-SWH-6F1U7U-14.4.14
  • VITA 66.5C and VITA 67.3C available for payload slots
  • Integrated ultra-low skew AUXCLK/REFCLK radial distribution
  • Chassis manager connector handles JTAG, maintenance ports (UARTs) and control

Optional Chassis Manager

  • Compatible with some Backplanes
  • SOSA-aligned and VITA 46.11 compliant
  • Xilinx UltraScale+ ZU5EG MPSoC running Linux for CHmC
    • Processing Subsystem (PS)
      • Quad core A53 ARM running at 1.2 GHz
      • Dual core R5 ARM
      • 4GB DDR4 DRAM
      • 128MB QSPI NOR
    • Programmable Logic subsystem (PL)
      • 256K System Logic cells in Programmable Logic
      • 18Mb of UltraRAM
      • 128MB QSPI NOR
      • Dual 128KB battery backed NV SRAM
  • Integrated JTAG access/control from chassis manager to each slot
    • External JTAG connection with SW selectable multiplexing from each slot
    • Xilinx JTAG over ethernet via Chassis Manager

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Technical Documents

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