WILD100 8-Slot 3U OpenVPX ATR – WC3A80

The rugged WILD100 8-Slot 3U OpenVPX SOSA™-Aligned Air Transport Rack (WC3A80) is a 100Gb Ethernet-enabled COTS 3U VPX Chassis, Backplane, and Chassis Manager. For a benchtop version of similar capability, see the WILD100 7-Slot 3U OpenVPX Chassis (WC3170).

It is VITA 65 compliant, SOSA-aligned, and designed and built in USA.

The rugged 100GbE SOSA-Aligned 3U VPX ATR includes a thermally-controlled Chassis, Backplane, and secure Chassis Manager.

The 8-slot forced-air, conduction-cooled unit incorporates slots for up to four conduction-cooled 3U VPX Payload Boards, 100GbE Switch, Clock Distribution Card, I/O-intensive SBC, and VITA 62 power supply.

The Chassis Manager is VITA 46.11/SOSA-aligned and utilizes a Xilinx UltraScale+ ZU5EG MPSoC.

See all of the Annapolis Chassis and Backplanes.

Chassis and Backplane

  • SOSA-aligned
  • Rugged top-loading, air-cooled Chassis with conduction-cooled slots
  • 8 3U OpenVPX Slots
    • 4 Payload Slots with 14.6.11 profile
    • 1 Clock Slot with 14.9.2 profile
    • 1 I/O-intensive SBC Slot with 14.2.16 profile
    • 1 40/100GbE Switch Slot with 14.4.14 or 14.4.15 profile
    • 1 VITA 62 Power Supply Slot – Standard or 12V-Heavy
  • Input power is 28VDC per MIL-STD-704F
  • 25 Gbps Line Rates on Data and Expansion Planes
    • 25/40/100Gb Ethernet
    • SDR/DDR/QDR/EDR Infiniband
    • Gen 3/4 PCI Express
    • Custom protocols up to 25Gbps per lane
  • VITA 66.5C and VITA 67.3C for payload slots
  • Integrated ultra-low skew AUXCLK/REFCLK radial distribution
  • Chassis manager connector handles JTAG, maintenance ports (UARTs) and control
  • Up to 2 MIL-DTL-38999 SOSA-aligned circular connectors with 19 RF connections each
  • LED Status Indicators
  • Chassis supports operation from -40 to 70 C and storage from -50 to 100 C ambient air
  • Rugged high velocity fan for cooling

Chassis Manager

  • SOSA-aligned and VITA 46.11 compliant
  • Xilinx UltraScale+ ZU5EG MPSoC running Linux for CHmC
    • Processing Subsystem (PS)
      • Quad core A53 ARM running at 1.2 GHz
      • Dual core R5 ARM
      • 4GB DDR4 DRAM
      • 128MB QSPI NOR
    • Programmable Logic subsystem (PL)
      • 256K System Logic cells in Programmable Logic
      • 18Mb of UltraRAM
      • 128MB QSPI NOR
      • Dual 128KB battery backed NV SRAM
  • Integrated JTAG access/control from chassis manager to each slot
    • External JTAG connection with SW selectable multiplexing from each slot
    • Xilinx JTAG over ethernet via Chassis Manager

Application Development

  • Standard Chassis Manager support delivered with all systems
    • IPMI Chassis Manager support with redundant IPMB
      • VITA 46.11 conformant and SOSA-aligned
      • Tier 2 Chassis Manager supporting Tier 1 and Tier 2
    • Chassis voltage and temperature sensor monitoring
    • Fan control and monitoring
    • UART support to payload cards
    • JTAG support to payload cards
  • Optional Full Board Support Package for Chassis Manager
    • Enables customization if needed of Zynq PS, PL
    • Provides fast and robust HDL-based application development environment

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