WILDSTAR Radial Clock Distribution Board – WP6C20

The WILDSTAR™ Radial Clock Distribution Board allows for synchronization of up to 20 ADC/DAC WFMC+ per Clock Board.

 

The WILDSTAR Radial Clock Distribution Board allows for synchronization of up to 20 ADC/DAC WFMC+ per Clock Board, with 10 differential radial REFCLK outputs, 10 differential radial AUXCLK outputs, and optional 20 single-ended clock outputs.

The Board is powered by a Xilinx Zynq UltraScale+ MPSoC EG Motherboard Controller.

It is 6U OpenVPX compliant and supported for air- or conduction-cooled environments.

General Features

  • Provides Capability to Synchronize up to 20 ADC/DAC WFMC+ per Clock Distribution Board
  • 10 Differential Radial REFCLK Outputs
  • 10 Differential Radial AUXCLK Outputs
  • Optional 20 Single-Ended Clock Outputs
  • RF Connections can be Front Panel or VITA 67.
  • Front Panel LEDs for Board Status (PLL Lock, Over Temperature, Power Good, etc)
  • Supports Clock Frequencies Higher than 4.5GHz
  • AUXCLK Outputs are Synchronized to REFCLK
  • Ultra-Low Phase Noise Distribution

Chassis Manager

  • Xilinx® Zynq® UltraScale+™ MPSoC EG Motherboard Controller (XCZU3EG)
  • Quad-core 64-bit ARM® Cortex-A53 running up to 1.5GHz
  • Dual-core 32-bit Cortex-R5 Real-time Processor running up to 600 MHz
  • Mali-400 MP2 Graphics Processing Unit running up to 667 MHz
  • 16nm FinFET+ Programmable Logic
  • 2 GB 32-bit DDR4 Memory running up to 1200 MHz
  • 4 GB SLC eMMC Bulk Storage for Filesystem
  • All the major functions of the ZYNQ+ can be controlled/monitored locally on ZYNQ+ (as a standalone board), remotely over 1Gb Ethernet or a combination of local and remote control/monitoring.
  • Primary functions/features:
    • Providing board health/sensor information including temperature of all FPGAs, board power, and individual power supply voltage/current/temperature. For information on additional monitoring/control capabilities contact factory.
    • Board controller for clock programming and board level configuration.
    • Remote API server. This enables a single point of control from remote device. These APIs (either run locally, remotely or both) can be used for runtime configuration of board resources such as FPGA or clock configuration and monitoring of board health sensors including FPGA temperature and board power.

Selectable Clock and Trigger Sources

  • Dynamically Selectable Clock Source
    • External RF Connection
    • Variable Frequency PLL Synthesizer
    • Fixed Frequency PLL
    • Fixed Frequency Oscillator
  • Dynamically Selectable Reference Clock Source
    • External RF Connection
    • Divided Clock
    • Fixed Frequency Oscillator
    • REFCLK (from VPX Backplane Bussed Connection)
  • Dynamically Selectable Trigger Source
    • External RF Connection
    • Divided Reference Clock
    • AUXCLK (from VPX Backplane Bussed Connection)
    • Front Panel Push Button
    • Software Initiated Trigger

Data Plane Extender

  • DP0, DP1, and DP2 can optionally be connected to a VITA 66.1 Connector with MT Ferrule for connecting multiple Backplanes
    Protocol Agnostic

Mechanical and Environmental

  • System Management (VITA 46.11) compatible MMC
  • 6U OpenVPX (VITA 65) Compliant, 1” VITA 48.1 spacing
  • Supports OpenVPX payload profile: MOD6-PAY-4F1Q2U2T-12.2.1-n
  • Integrated EMI/Crosstalk Shield and Board Stiffener
  • Commercial and Industrial Temperatures Available
  • Air Cooled and Conduction Cooled supported
  • Diagnostic monitoring and configuration
  • Current, Voltage and Temperature Monitoring Sensors
  • Hot Swappable when configured for EAC1

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Technical Documents

For additional documentation, please contact your Sales Representative.

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