FPGA Signal Processing Seminar & Open House

It's our 37th year in business - come learn and celebrate with us!

Date: Thursday, November 7, 2019
Location: Annapolis Micro Systems
What: Attend either or both of:

  • 9am-3pm – SEMINAR (see detail below)
  • 3pm-6pm – OPEN HOUSE (see detail below)

Cost: FREE
NOTE: We are sensitive to some people’s need to keep their company or program anonymous, so there will be no disclosure of the registration list for this event, and attendee privacy will be maintained. However, all attendees must register using the following form.

Seminar Detail (9am-3pm)

Featuring short informative presentations/demos on these topics:

  1. SOSA™ Standardization Update: The Latest from the Hardware Working Group
    • Jay Grandin, VP of Product Development & SOSA Hardware Working Group Member
  2. Machine Learning & Artificial Intelligence in Aerospace and Defense
    • Jason Vidmar, Xilinx Military and Satellite Communications System Architect
  3. Demo: Validation Tools for Baseboards and Mezz Cards
    • Kenny Toma, VP of Development Flow
  4. Case Study: Conquering Phased Array Digital Beamforming via FPGAs & 100GbE
    • Mark Holland, Director of Application Development
  5. High Speed Conversion & RF Transceivers for Signal Processing Applications
    • TBD, Analog Devices
  6. What’s New & In the Pipeline? An Innovation Update
    • Noah Donaldson, CTO
  7. Demo: Ultra-Wide Bandwidth Signal Processing with Annapolis’ New 6XBU 6U Baseboard
    • Mark Holland, Director of Application Development
  8. What's New in Annapolis' Board Support Package
    • Rhett Hudson, VP of Software Development

The Seminar is capped at 30 attendees. Note that topics may be modified based on attendee interest.

Open House Detail (3-6pm)

Includes finger foods, drinks, and:

The Open House is capped at 50 attendees.

All attendees must register below.

Seminar & Open House RSVP
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