WILDSTAR 3XVR 3U OpenVPX FPGA Processor – WS3XVR

The WILDSTAR 3XVR FPGA Processor is 100GbE-enabled, SOSA-aligned, and it leverages the processing and A/D & D/A converting power of an AMD Versal RF FPGA.

Want the same Direct RF sampling capability in an even smaller form factor? See all of our Small Form Factor Solutions.

These SOSA-aligned Plug-In Cards (PIC) offer many channels and high ADC/DAC sample rates that are integrated into the FPGA. Choose from one of four Versal RF FPGAs: VR1602, VR1652, VR1902, or VR1952.

This board also includes an Analog Interface Mezzanine Site. This can be populated with Annapolis or 3rd party/customer-designed RF Cards for front-end personalization (e.g. pre-filtering or analog conditioning) for applications of interest.

Annapolis’ powerful BSP options include 40/100GbE IP and Linux support.

Review other OpenVPX 3U and Xilinx FPGA boards.

 

 

General Features

  • One Versal™ RF Series VR1602/VR1652/VR1902/VR1952 FPGA
    • Up to 3,976 DSP58 and 2,473,800 logic cells
    • Up to 126 AI engine tiles
    • Four 32-bit LPDDR5 DRAM ports running up to 3732 MT/s
    • Dual-core 64-bit ARM Cortex-A72 running up to 1.4GHz
    • Dual-core 32-bit Cortex-R5F real-time processor running up to 450MHz
  • Optional Front Panel RS422/RS485 GPIO interface
  • Optional 0/2×40/100G Optical Transceivers to VITA 66 Backplane Interface
  • VITA 46.11/SOSA IPMC Support
  • Supports Annapolis or 3rd party/customer-designed Analog Interface Card for RF conditioning
  • Multiple levels of hardware and software security

ADC & DAC I/O

  • VR1602
    • ADC: 16 channels at 8 GSps sample rate with 14-bit resolution
    • DAC: 16 channels at 16 GSps sample rate with 14-bit resolution
  • VR1652
    • ADC: 4 channels at 32 GSps sample rate with 14-bit resolution
    • DAC: 8 channels at 16 GSps sample rate with 14-bit resolution
  • VR1902
    • ADC: 16 channels at 8 GSps sample rate with 14-bit resolution
    • DAC: 16 channels at 16 GSps sample rate with 14-bit resolution
  • VR1952
    • ADC: 8 channels at 32 GSps sample rate with 14-bit resolution
    • DAC: 16 channels at 16 GSps sample rate with 14-bit resolution
  • Backplane optical and RF support with VITA 66/67
  • HSS connections can support protocols such as 10/40/100Gb Ethernet and Aurora or user designed protocols. Some HSS interfaces also support PCIe using FPGA hard blocks.

Mechanical and Environmental

  • 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.2 spacing
  • Supports OpenVPX payload profile SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n
  • Available with 85°C ambient air temperature or card edge support and -55°C power-on
  • Available with -65°C to 105°C storage temperature
  • Air, Air-Flow-Through or Conduction Cooled
  • Only requires +12V and +3.3VAUX from backplane
  • Developed in alignment with the SOSA™ Technical Standard
  • RT3 backplane connectors for 100G support

Application Development

  • Full Board Support Package for fast and easy Application Development
  • Includes source for all provided software components and examples on Versal PEs
  • Open CoreFire™ support
    • HDL generation
  • Three development flow paths:
    • Traditional RTL development flow
      • HDL/IPI -> Vivado™ -> PetaLinux project -> Bitstream
    • *NEW* Dynamic Function eXchange (DFX) RTL development flow
      • Includes abstract shell approach which avoids PetaLinux rebuilds on iterations
      • Design refactors and testing iterations significantly sped up
      • CIPs function remains active while fabric is reloaded
    • *NEW* Vitis™ Platform Project development flow

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Technical Documents

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