WILDSTAR 3XVC 3U OpenVPX FPGA Processor – WS3XVC
The WILDSTAR 3XVC integrates AMD's Versal™ Premium VP1702 FPGA and features ultra-high-speed RT4 backplane connectors for up to 200G support. It is also SOSA-aligned, and highly rugged and thermally-controlled.
Need the same Versal power and SOSA alignment in a 6U VPX form factor? See the WILDSTAR 6XV4 6U OpenVPX Board.
These SOSA-aligned Plug-In Cards (PIC) include one Versal Premium VP1702 FPGA and have five 32-bit LPDDR4 DRAM ports running up to 3732 MT/s.
If front panel and/or backplane IO is required, Annapolis offers extraordinary density, bandwidth and analog conversion choices. Each card has a next generation mezzanine site that is optimized for JESD-based ADCs and DACs. Based on FMC/FMC+ specification, it allows larger form factor cards for higher IO density. VITA 66/67 optical/RF backplane support is included.
There is also an on-board dual-core ARM CPU running up to 1.4 GHz which can be used for local application requirements. It is accessible over backplane PCIe or Ethernet and provides dedicated AXI interfaces to all FPGAs. It is also used to query board health like FPGA temperature and power. It is connected to the OpenVPX control plane via 1GbE.
The air-cooled 3XVC is hot swappable, allowing for more system reliability. This feature is unique to Annapolis and was developed because our experience with OpenVPX systems has shown it invaluable, so a whole chassis does not need to be shutdown to remove a single board.
Review other OpenVPX 3U and Xilinx FPGA boards.
General Features
- One Versal™ Premium VP1702 FPGA
- Up to 10,896 DSP Slices and 5,557,720 logic cells
- Up to 541 Mb of High Bandwidth, Low Latency UltraRAM
- Five 32-bit LPDDR4 DRAM ports running up to 3732 MT/s
- Dual-core 64-bit ARM Cortex-A72 running up to 1.4GHz
- Dual-core 32-bit Cortex-R5F real-time processor running up to 450MHz
- Optional Front panel RS422/RS485 GPIO interface
- Optional 3×40/100G Optical Transceivers to VITA 66 Backplane Interface
- Multiple levels of hardware and software security
Next Generation “WILD Mezzanine Card HSS” (WMC-H) Site
- Optimized for JESD-based ADCs and DACs or Optical Transceivers
- For High Bandwidth Applications
- Annapolis Mezzanine products with “WH” prefix
- SOSA Aligned backplane I/O
- Optimized for VITA 66/67 interfaces
- Optimized for cooling
- Allows larger form factor cards for higher IO density
- Available options:
Mechanical and Environmental
- 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.2 spacing
- Supports OpenVPX payload profile:
- SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n
- SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-n (no P2A connectivity)
- Available with 85°C ambient air temperature or card edge support and -55°C power-on
- Available with -65°C to 105°C storage temperature
- Air, Air-Flow-Through or Conduction Cooled
- Only requires +12V and +3.3VAUX from backplane
- Developed in alignment with the SOSA™ Technical Standard 1.0
- RT4 backplane connectors for up to 200G support
Application Development
- Full Board Support Package for fast and easy Application Development
- Includes source for all provided software components and examples on Versal PEs
- Open CoreFire™ Support
- Graphical RTL generation of algorithm blocks
- Feeds RTL development flow
- Boot methodology and development flow path options:
- Dynamic Function eXchange (DFX) via Abstract Shell Configuration
- RTL design of the Reconfigurable Module (RM)
- Design iteration speed up with reduced compile times
- CIPS stands while RM region can be reloaded
- Monolithic Configurations
- Traditional full RTL design
- Dynamic Function eXchange (DFX) via Abstract Shell Configuration
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