Up to two identical Xilinx® Kintex or Virtex UltraScale FPGAs with choice of Kintex™ UltraScale KU085 or KU115 or Virtex™ UltraScale VU125 FPGAs. Up to 80 GB of DDR4 DRAM for up to 116 GB/s of DRAM bandwidth. Up to 2.5 million logic cells and 5.4 million multiplier bits per board.

These FPGA boards include two Xilinx® Kintex UltraScale or Virtex™ UltraScale FPGAs with High Speed Serial connections performing up to 25+ Gbps.  On each Compute Processing Element (CPE) FPGA there are two 48-bit and 80-bit DDR4 DRAM interfaces clocked up to 1200 MHz.

There is also an on-board dual ARM CPU running up to 766 MHz which can be used for local application requirements without using PCIe bandwidth.  It is accessible over PCIe and also has dedicated AXI interfaces to all FPGAs.  There is an RJ45 Ethernet port and UART for ease of application development.  The on-board CPU can also utilize the PCIe bus back to host CPU for Ethernet and control.

There are 4 QSFP28s for external IO, each capable of 40GbE with Kintex parts or 100GbE with Virtex parts.

PCIe boards connect to the host system via a Gen 3 PCI Express switch which provides a x16 interface to the host (up to 16 GB/s) and x8 Gen3 interfaces to each FPGA (up to 8 GB/s). There is also plenty of on-board inter-FPGA HSS connections for data movement.

To ensure safe and reliable processing, WILDSTAR UltraK for PCIe boards come equipped with a proactive thermal management system. Sensors across the board monitor power and temperature, with automatic shutdown capability to prevent excessive heat buildup. WILDSTAR UltraK for PCIe boards are built with a rugged, durable design.

Review other PCIe FPGA boards or other Xilinx FPGA boards.


General Features

  • Up to Two identical Xilinx® Kintex® or Virtex® UltraScale™ FPGAs with choice of:
    • Kintex UltraScaleTM KU085 or KU115 FPGAs
      • Up to 11,040 DSP48E1 Slices per board
      • Up to 2,322,000 logic cells per board
      • GTH transceivers operating up to 16.3 Gbps
    • Virtex UltraScale VU125 FPGAs
      • Up to 2400 DSP48E1 Slices per board
      • Up to 2,506,000 logic cells per board
      • GTH transceivers operating up to 16.3 Gbps
      • GTY transceivers operating up to 30.5 Gbps
      • Four or Six 100GbE Integrated IP Cores per FPGA
    • Can be ordered with 1 or 2 CPE FPGAs
    • Hard 8x PCIe Gen3 endpoint for DMA and register access
    • Both FPGAs have same pinout and are bitstream compatible
    • FPGAs programmable from attached flash or Annapolis provided software API
    • 20-nm copper CMOS process
    • DDR4 DRAM on all FPGAs running up to 2400 MT/s
      • Two 48-bit ports
        • Up to 12 GB/FPGA, up to 24 GB/board
        • Up to about 25 GB/s per FPGA
      • Two 80-bit ports
        • Up to 36 GB/FPGA, up to 72 GB/board
        • Up to about 40 GB/s per FPGA
        • ECC optional
  • PLX PCI Express Gen3 Switch
    • Up to 16x Gen3 motherboard interface
    • 8x Gen3 interface to each FPGA

Board Configuration/Control

  • Xilinx Zynq-7000 SoC
    • Dual core ARM Cortex-A9 running up to 766 MHz
    • 1 GB DDR3 memory and
    • 4GB eMMC bulk storage
    • USB UART and 10/100/1000 BASE-T connections
  • Provides dedicated AXI bus to FPGA for register access without requiring PCIe interface
  • Allows for on-board monitoring/control without consuming PCIe bandwidth

Front Panel I/O

  • Quad QSFP28 interface
    • Up to 4×25 Gbps+ per QSFP with Virtex FPGAs (for 100GbE)
    • Up to 4×16 Gbps+ per QSFP with Kintex FPGAs (for 40GbE)
      • Annapolis provides 40GbE IP with board
  • Simultaneous Optics and ADC/DAC use with two slots
  • Protocol Agnostic HSS connections support 10/40/100 Gb Ethernet, IB capable, AnnapMicro protocol and user designed protocols

Application Development

  • Open Project Builder Application Design Suite
    • Full Board Support Package for Fast and Easy Application Development
    • Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
    • Develop in GUI environment or create VHDL and use HDL environment
    • Built-in Debugger for Hardware in the loop Debugging
    • Communication Cores Included (10/40Gb Ethernet and AnnapMicro Protocol cores)
    • VHDL Model includes Source Code for Hardware Interfaces
    • Supports High-Level Synthesis (HLS) Design Flow
  • JTAG Access through RTM, Ethernet, or PCIe
  • Board control and status monitoring can be local (stand alone), remote (via Ethernet or PCIe) or hybrid (both local and remote)

System Management

  • System Management using PCIe Intelligent Platform Management Interface (IPMI)
  • Diagnostic monitoring and configuration
  • Current, Voltage and Temperature Monitoring Sensors
  • Drivers and APIs for Host Systems running Windows and Linux are included

Mechanical and Environmental

  • 10.5” length for wider chassis compatibility
    • Does not require a “Full Length” slot
  • Integrated Heat Sink and Board Stiffener
  • External +12V Power Connector

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Technical Documents

For additional documentation, please contact your Sales Representative.

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