One Xilinx® Kintex® UltraScale™ KU085 or KU115 FPGA with up to 18 MB of QDR-IV SRAM for 28.8 GB/s of SRAM bandwidth. Up to 1.2 million logic cells and 2.68 million multiplier bits per board.  Also features WFMC+ mezzanine card with stacking support, on-board Zynq Dual ARM CPU and PCIe Gen3 Switch.

Xilinx Kintex UltraScale SRAM OpenVPX 3U FPGA Board

These FPGA boards include 1 Xilinx® Kintex® UltraScale™ FPGA with 64 High Speed Serial connections performing up to 13.1 Gbps. There is one 72-bit QDR-IV SRAM interface clocked up to 800 MHz.

If IO is required, Annapolis offers extraordinary density, bandwidth and analog conversion choices. Each card has one WILD FMC+ (WFMC+) next generation IO site based on FMC/FMC+ specification.  While accepting standard FMC and FMC+ cards (complies to FMC/FMC+ specification) it also allows larger form factor Annapolis WFMC+ cards for higher IO density.  WFMC+ also supports additional LVDS IO (100) for higher density ADC and DAC solutions as well as stacking (2 IO cards per site) when at least one card is WFMC+.  WFMC+ also brings the total available HSS up to 32 lanes for even more IO bandwidth.

There is also an on-board dual ARM CPU running up to 766 MHz which can be used for local application requirements.  It is accessible over backplane PCIe or Ethernet and provides dedicated AXI interfaces to all FPGAs.  It is also used to query board health like FPGA temperature and power. It is connected to the OpenVPX control plane via 1GbE.

There is an on-board PCI Express Gen3 switch that provides connectivity between the FPGA, backplane data plane connections and Zynq CPU.  With 2 backplane 4x Gen3 PCIe ports, it is possible to “daisy chain” slots together to create a PCIe bus without the need for a separate switch.

In addition, there are 9 backplane HSS connections. With included High Speed Serial (HSS) FPGA cores (including 40GBASE-KR), there is up 20 GB/s of bandwidth on the VPX expansion plane which can go directly to other VPX cards, a switch or RTM, depending on backplane topology.  When using 40GBASE-KR, there is the added reliability of Forward Error Correction (FEC) to achieve a much lower Bit Error Rate (BER).

WILDSTAR UltraK FPGA boards are hot swappable allowing for more system reliability. This feature is unique to Annapolis and was developed because our experience with OpenVPX systems has shown it invaluable so a whole chassis does not need to be shutdown to remove a single board.

There are also plenty of user backplane signals available on the Annapolis 6U Rear Transition Module (RTM) such as LVDS, FPGA HSS, IRIG, Ethernet and clocking. RTM HSS is also capable of 10Gbps signaling and can support multiple channels of 40GbE.

Review other OpenVPX 3U and Xilinx FPGA boards.


General Features

  • One Xilinx® Kintex® UltraScaleTM KU085 or KU115 FPGA
    • Up to 5,520 DSP48E1 Slices per board
    • Up to 1,161,000 logic cells per board
    • GTH transceivers operating up to 16.3 Gbps
    • Hard 8x PCIe Gen3 endpoint for DMA and register access
    • FPGAs programmable from attached flash or Annapolis provided software API
    • 20-nm copper CMOS process
    • For XCKU060 FPGA support contact factory
    • QDR-IV SRAM ports running up to 1866 MT/s
      • One 72-bit port
      • Up to 16 MB per FPGA/board
      • Up to about 16.8 GB/s
      • ECC optional
  • Xilinx® Zynq-7000 SoC
    • Dual core ARM Cortex-A9 running up to 766 MHz
    • 1 GB DDR3 memory and 4GB eMMC bulk storage for filesystem
    • Configurable as either PCIe root complex or endpoint
    • Provides dedicated AXI bus to FPGA for register access without requiring PCIe interface
  • PLX PCI Express Gen3 Switch
    • Allows data plane “chaining” of PCIe bus between adjacent slots. No dedicated PCIe switch slot needed.
    • Allows access from a single PCIe connection to both SoC CPU and FPGA

OpenVPX Backplane I/O

  • Nine High Speed Serial IO lanes to VPX Backplane for 22.5 GB/s of Full Duplex Bandwidth
  • Two PCIe Gen3 4x Connections to VPX Backplane
  • 24 LVDS lines to VPX Backplane
  • Backplane Protocol Agnostic connections support 10/40Gb Ethernet, IB capable, AnnapMicro protocol and user designed protocols
  • External clock and IRIG-B Support via Backplane
  • 10/100/1000BASE-T support for Zynq with on-board magnetics
  • Radial Backplane Clock Support for OpenVPX backplane signals AUXCLK and REFCLK
    • Allows points-to-point, very high quality backplane connections to payload cards
    • Allows a system reference clock and trigger from backplane to synchronize and clock compatible ADC/DAC mezzanine cards without front panel connections needed
    • Allows 1000s of analog channels across many backplanes/chassis to be synchronized via backplane

System Management

  • System Management using Intelligent Platform Management Interface (IPMI)
  • Diagnostic monitoring and configuration
  • Current, Voltage and Temperature Monitoring Sensors
    • Hot Swappable (exclusive to WILDSTAR OpenVPX EcoSystem)

Front Panel I/O

  • Wild FMC+ (WFMC+) next generation IO site based on FMC+ specification
    • Accepts standard FMC and FMC+ cards (complies to FMC+ specification)
    • Allows larger form factor Annapolis cards for higher IO density
    • Supports additional LVDS IO for higher density ADC and DAC solutions
    • Supports stacking (2 IO cards per site) when at least one card is WFMC+
    • Up to 32 High Speed Serial and 100 LVDS connections to FPGA
  • Simultaneous Optics and ADC/DAC use with two slots
  • Protocol Agnostic HSS connections support 10/40/100 Gb Ethernet, IB capable, AnnapMicro protocol and user designed protocols
  • Micro USB connector for CPU serial port (uses USB to UART bridge chip)

Application Development

  • Open Project Builder Application Design Suite
    • Full Board Support Package for Fast and Easy Application Development
    • Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
    • Develop in GUI environment or create VHDL and use HDL environment
    • Built-in Debugger for Hardware in the loop Debugging
    • Communication Cores Included (10/40Gb Ethernet and AnnapMicro Protocol cores)
    • VHDL Model includes Source Code for Hardware Interfaces
    • Supports High-Level Synthesis (HLS) Design Flow
  • VHDL BSP packages including full synthesis and simulation support
  • IOPE JTAG Access through RTM, Ethernet, or Zynq PCIe
  • Board control and status monitoring can be local (stand-alone), remote (via Ethernet or PCIe) or hybrid (both local and remote)

Mechanical and Environmental

  • 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.1 spacing
  • Supports OpenVPX payload profile:MOD3-PAY-2F4F2U-16.2.10-n
  • Integrated Heat Sink and Board Stiffener
  • Available in Industrial Temperature Grades
  • Air or Conduction Cooled
  • RTM available for additional I/O

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