WILDSTAR 6XBU 6U OpenVPX FPGA Processor – WB6XBU

This breakthrough Ultra-Wide-Bandwidth (UWB) FPGA Board features a super-high-performance digitizer and processor in a single rugged 6U OpenVPX board. It is designed to handle full ADC input bandwidths in the most challenging data acquisition, processing, and storage applications.

See all of the Annapolis FPGA Boards.

WILDSTAR 6XBU boards include 2 Xilinx Virtex UltraScale+ XCVU9P or XCVU13P (10GB of DDR4 DRAM per FPGA) and one Xilinx Zynq UltraScale+ MPSoC Quad A53/Dual R5 ARM Motherboard Controller.

Digitization is built in: 2 channels @32GSps & 4 channels @16GSps. Resolution is 10 bits and analog input bandwidth is 9GHz per channel.

Four optional 4x FireFly optical transceivers support  VITA 66 connectivity.

Air or conduction cooled. Available with +70C ambient temperature support and -40C power-on.

Hot swappability in air-cooled environments allows for more system reliability. This feature is unique to Annapolis and was developed because our experience with OpenVPX systems has shown it invaluable for maintaining operation during a board change.

Developed in alignment with the SOSA™ Technical Standard.

Review other OpenVPX 6U and Xilinx FPGA boards.

 

Two Xilinx® Virtex® Ultrascale+™ FPGAs

  • Supports XCVU9P/XCVU13P FPGAs
    • Up to 24,576 DSP48E1 Slices and 7,560,000 logic cells
    • Up to 720 Mb of High Bandwidth, Low Latency UltraRAM
    • Gen4 PCIe, 150G Interlaken and 100Gb Ethernet Hard Cores
    • Two 80-bit, 5 GB DDR4 DRAM ports
    • GTY transceivers operating up to 32.75 Gb/s
    • FPGAs programmable from attached flash, JTAG or Annapolis API
    • 16nm FinFET+ process

One Xilinx® Zynq® UltraScale+™ MPSoC Quad A53/Dual R5 ARM Motherboard Controller

  • Processing Subsystem (PS)
    • Quad-core 64-bit ARM® Cortex-A53
    • Dual-core 32-bit Cortex-R5 real-time processor
    • Mali-400 MP2 graphics processing unit
    • One 64-bit, 4 GB DDR4 memory
    • 4 or 32 GB SLC SATA bulk storage for filesystem
    • 256Kb user SPI FRAM
  • Programmable Logic (PL)
    • Up to 2928 DSP slices or 1,143,00 logic cells
    • Up to 36Mb of High Bandwidth, Low Latency UltraRAM
    • Gen4 PCIe, 150G Interlaken and 100Gb Ethernet Hard Cores
    • GTH/GTY transceivers operating up to 32.75 Gb/s
    • 256Kb user SPI FRAM
  • 16nm FinFET+ process
  • Provides dedicated AXI bus to IOPE FPGAs for register access
  • Board support enabling user customization of ZYNQ+ design
  • Multiple levels of hardware and software security

Backplane I/O

  • Up to 38 High Speed Serial to VPX Backplane for up to 182 GB/s
  • Two 1/10GbE and two 1GbE BASE-T to VPX Control Plane
  • 32 LVDS lines to VPX P5, 8 from each IOPE and 16 from HPE
  • 8 Single Ended 3.3V I/O to VPX Backplane P5 from HPE
  • RS-232, RS-422 or RS-485 interface to ZYNQ HPE
  • Backplane Protocol Agnostic connections support 10/40Gb Ethernet, IB capable, AnnapMicro protocol and user designed protocols
  • External clock and IRIG-B Support via Backplane
  • Radial Backplane Clock Support for OpenVPX backplane signals AUXCLK and REFCLK
    • Allows points-to-point, very high-quality backplane connections to payload cards
    • Allows a system reference clock and trigger from backplane to synchronize and clock ADCs without front panel connections needed
    • Allows 1000s of analog channels across many backplanes/chassis to be synchronized via backplane

ADC Performance

  • ADC Inputs
    • 2 channels at 32GSps
    • 4 channels at 16GSps
  • Analog Specs
    • Resolution: 10 bits
    • SFDR: ~60 dBc
    • ENOB: ~7 bits
    • Analog Input Bandwidth: 9GHz per channel

Front Panel I/O

  • Eleven 50Ω Front Panel RF
    • Four Analog ADC Inputs
    • Two ADC Clock Inputs
    • One ADC Clock Output
    • One Reference Clock Input
    • One Reference Clock Output
    • One Trigger control signal Input
    • One IRIG signal Input
  • Four optional 4x FireFly Optical transceivers (optional VITA 66)
  • Simultaneous Optics and ADC use
  • USB UART and USB-C. Both can optionally be directed to backplane

Application Development Board Support Package

  • Open Project Builder Application Design Suite
    • Full Board Support Package for Fast and Easy Application Development
    • Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
    • Develop in GUI environment or create VHDL and use HDL environment
    • Built-in Debugger for Hardware in the loop Debugging
    • Communication Cores Included (10/40Gb Ethernet, AnnapMicro Protocol)
    • VHDL Model includes Source Code for Hardware Interfaces
    • Supports High-Level Synthesis (HLS) Design Flow
  • VHDL BSP packages including full synthesis and simulation support
  • Support for Mathworks HDL Coder™ generated IP
  • IOPE JTAG Access through RTM or Ethernet
  • Board control and status monitoring can be local (stand-alone), remote (via Ethernet) or hybrid (both local and remote)

Mechanical and Environmental

  • 6U OpenVPX Compliant 1.0″ spacing
  • Available with +70°C ambient temperature support and -40°C power-on
  • Optional VITA 66/67 support
  • Integrated Heat Sink and Board Stiffener
  • Available in Industrial Temperature Grades
  • Air or Conduction Cooled
  • RTM available for additional I/O
  • Hot Swappable with air cooled variants
  • Only requires +12V and +3.3VAUX from backplane
  • Developed in alignment with the SOSA™ Technical Standard
  • RT3 backplane connectors for 100G support

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Technical Documents

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