WILDSTAR 3XV1 3U OpenVPX FPGA Processor – WB3XV1

The WILDSTAR 3XV1 integrates Xilinx's new Versal™ Premium VP1202 or VP1502 FPGA. It is 100GbE-enabled, SOSA-aligned, and highly rugged and thermally-controlled.

Need the same Versal power and SOSA alignment and 100GbE capability in a 6U VPX form factor? See the WILDSTAR 6XV2 6U OpenVPX Board.

These FPGA boards are SOSA-aligned Plug-In Cards (PIC). They include one Versal Premium VP1202/VP1502 FPGA and have eight 32-bit LPDDR4 DRAM ports running up to 3700 MT/s.

If front panel and/or backplane IO is required, Annapolis offers extraordinary density, bandwidth and analog conversion choices. Each card has a next generation mezzanine site that is optimized for JESD-based ADCs and DACs. Based on FMC/FMC+ specification, it allows larger form factor cards for higher IO density. VITA 66/67 optical/RF backplane support is included.

There is also an on-board quad ARM CPU running up to 1.4 GHz which can be used for local application requirements.  It is accessible over backplane PCIe or Ethernet and provides dedicated AXI interfaces to all FPGAs.  It is also used to query board health like FPGA temperature and power. It is connected to the OpenVPX control plane via 1GbE.

The air-cooled 3XV1 is hot swappable, allowing for more system reliability. This feature is unique to Annapolis and was developed because our experience with OpenVPX systems has shown it invaluable, so a whole chassis does not need to be shutdown to remove a single board.

Review other OpenVPX 3U and Xilinx FPGA boards.

General Features

  • One Versal Premium VP1202/VP1502 FPGA
    • Up to 7,440 DSP Slices and 3,763,480 logic cells
    • Up to 366 Mb of High Bandwidth, Low Latency UltraRAM
    • Eight 32-bit LPDDR4 DRAM ports running up to 3700 MT/s
    • Dual-core 64-bit ARM® Cortex-A72 running up to 1.4GHz
    • Dual-core 32-bit Cortex-R5F real-time processor running up to 600MHz
  • Multiple levels of hardware and software security

Next Generation Mezzanine Site

  • Optimized for JESD based ADC and DACs
  • SOSA Aligned backplane I/O
  • Optimized for VITA 66/67 interfaces
  • Optimized for cooling
  • Allows larger form factor cards for higher IO density
  • Based on FMC+
  • Available options:
    • Analog Devices MXFE: 2TX (12GSps)/4RX (6GSps)
    • Analog Devices MXFE: 1TX (12GSps)/8RX (4GSps)
    • Jariet Electra-MA: 2TX (64GSps)/2RX (64GSps)
    • Xilinx RFSoC: 2TX (5GSps)/8RX (5GSps)
    • Xilinx RFSoC: 4TX (5GSps)/4RX (5GSps)
    • Others covered under NDA. Contact Factory for more information.

Mechanical and Environmental

  • 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.2 spacing
  • Supports OpenVPX payload profile:
    • SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n (SOSA Primary)
  • Available with 85C ambient air temperature or card edge support and -55C power-on
  • Available with -65C to 105C storage temperature
  • Air, Air-Flow-Through or Conduction Cooled
  • Only requires +12V and +3.3VAUX from backplane
  • Developed in alignment with the SOSA™ Technical Standard 1.0
  • RT3 backplane connectors for 100G support

Application Development

  • CoreFire Next Application Design Suite
    • Full Board Support Package for Fast and Easy Application Development
    • Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
    • Develop in GUI environment or create VHDL and use HDL environment
    • Built-in Debugger for Hardware in the loop Debugging
    • Supports High-Level Synthesis (HLS) Design Flow
  • VHDL BSP packages including full synthesis and simulation support
  • Communication Cores Included (10/40Gb Ethernet and AnnapMicro Protocol cores)
  • IOPE JTAG Access through backplane
  • Board control and status monitoring can be local and/or remote (via Ethernet)

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Technical Documents

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