WILDSTAR 3XS0 3U OpenVPX FPGA Processor – WB3XS0

The WILDSTAR 3XS0 is our standard 3U RFSoC FPGA Board. It is 100GbE-enabled, SOSA-aligned, and it leverages the processing and A/D & D/A converting power of a Gen 3 Xilinx UltraScale+™ RFSoC FPGA.

Need more RFSoC processing capability? See the dual RFSoC WILDSTAR 3XR0 3U OpenVPX Board.

Need the same SOSA-alignment and 100GbE capability in a 6U VPX form factor? See the WILDSTAR 6XB2 6U OpenVPX Board.

These FPGA boards utilize all eight ADC and DAC channels of the powerful Gen 3 Zynq® UltraScale+™ RFSoC. Maximum sample rates are 5.0+GSps ADC and 10.0+GSps DAC, with 14 bit resolution.

Backplane RF is supported via VITA 67.

The board is highly rugged and thermally-controlled, with options for air, air-flow-through, or conduction cooling.

The 3XS0 is hot swappable in air-cooled environments, allowing for more system reliability. This feature is unique to Annapolis and was developed because our experience with OpenVPX systems has shown it invaluable so a whole chassis does not need to be shutdown to remove a single board.

It was developed in alignment with the SOSA™ Technical Standard, supporting SOSA primary payload profile SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n

Annapolis’ powerful BSP options include 40/100GbE IP and both VxWorks 7 and Linux support.

Review other OpenVPX 3U and Xilinx FPGA boards.

General Features

  • One Gen 3 Zynq® UltraScale+™ RFSoC FPGAs (XCZU47DR). Other configurations also available – contact factory for part number options.
    • Quad-core 64-bit ARM® Cortex-A53
    • Dual-core 32-bit ARM® Cortex-R5F
    • Up to 2.8 Mb of UltraRAM
    • 16GB of DDR4 DRAM
  • VITA 46.11/SOSA IPMC Support

ADC & DAC I/O

  • ADC
    • Channels: 8
    • Max Sample Rate: 5.0GSps
    • Resolution: 14 bit
  • DAC
    • Channels: 8
    • Max Sample Rate: 10.0GSps
    • Resolution: 14 bit
  • Backplane RF support with VITA 67
  • HSS connections can support protocols such as 10/40/100Gb Ethernet and Aurora or user designed protocols. Some HSS interfaces also support PCIe using FPGA hard blocks

Mechanical and Environmental

  • 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.1 or 1.5” VITA 48.8 (AFT) spacing
  • Supports SOSA primary payload profile: SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n
  • Available with 85° C ambient air temperature or card edge support and -55°C power-on
  • Available with -65° C to 105° C storage temperature
  • Air, Air-Flow-Through or Conduction Cooled
  • Only requires +12V and +3.3VAUX from backplane
  • Developed in alignment with the SOSA™ Technical Standard
  • RT3 backplane connectors for 100G support

Application Development

  • Open Project Builder Application Design Suite
    • Full Board Support Package for Fast and Easy Application Development
    • Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
    • Develop in GUI environment or create VHDL and use HDL environment
    • Built-in Debugger for Hardware in the loop Debugging
    • Supports High-Level Synthesis (HLS) Design Flow
  • VHDL BSP packages including full synthesis and simulation support
  • Communication Cores Included (10/40Gb Ethernet and AnnapMicro Protocol cores)
  • IOPE JTAG Access through RTM or Ethernet
  • Board control and status monitoring can be local and/or remote (via Ethernet)

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Technical Documents

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