WILDSTAR 3AA2 3U OpenVPX FPGA Processor – WB3AA2

The WILDSTAR 3AA2 integrates Intel's powerful Agilex M-Series AGM 032 or AGM 039 FPGA. It is 100GbE-enabled, SOSA-aligned, and highly rugged and thermally-controlled.

Need the same SOSA-alignment and 100GbE capability in a 6U VPX form factor? See the WILDSTAR 6XB2 6U OpenVPX Board.

These SOSA-aligned Plug-In Cards (PIC) include one Agilex M-Series AGM 032/039 FPGA and have one 72-bit DDR4 DRAM port running up to 3733 MT/s.

If front panel and/or backplane IO is required, Annapolis offers extraordinary density, bandwidth and analog conversion choices. Each card has a next generation mezzanine site that is optimized for JESD-based ADCs and DACs. Based on FMC/FMC+ specification, it allows larger form factor cards for higher IO density. VITA 66/67 optical/RF backplane support is included.

The air-cooled 3AA2 is hot swappable, allowing for more system reliability. This feature is unique to Annapolis and was developed because our experience with OpenVPX systems has shown it invaluable, so a whole chassis does not need to be shutdown to remove a single board.

Review other OpenVPX 3U and Xilinx FPGA boards.

General Features

  • One Agilex M-Series AGM 032/039 FPGA
    • Up to 3,851,520 logic elements
    • Up to 1,305,600 adaptive logic modules
    • Up to 18,960 M20K blocks
    • Up to 370 M20K Mbits
    • Up to 65,280 MLAB counts
    • Up to 40 MLAB Mbits
    • 16/32 HBM2e DRAM GBytes
    • Up to 12,300 variable precision DSP blocks
    • Up to 24,600 18×19 multipliers
  • Multiple levels of hardware and software security

Next Generation Mezzanine Site

  • Optimized for JESD based ADC and DACs
  • SOSA Aligned backplane I/O
  • Optimized for VITA 66/67 interfaces
  • Optimized for cooling
  • Allows larger form factor cards for higher IO density
  • Based on FMC+
  • Available options:
    • Analog Devices MXFE: 2TX (12GSps)/4RX (6GSps)
    • Analog Devices MXFE: 1TX (12GSps)/8RX (4GSps)
    • Jariet Electra-MA: 2TX (64GSps)/2RX (64GSps)
    • Xilinx RFSoC: 2TX (5GSps)/8RX (5GSps)
    • Xilinx RFSoC: 4TX (5GSps)/4RX (5GSps)
  • Others covered under NDA. Contact Factory for more information.

Mechanical and Environmental

  • 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.1 spacing
  • Supports OpenVPX payload profile:
    • SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n (SOSA Primary)
    • SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-n (SOSA Secondary)
  • Available with 85C ambient air temperature or card edge support and -55C power-on
  • Available with -65C to 105C storage temperature
  • Air, Air-Flow-Through or Conduction Cooled
  • Only requires +12V and +3.3VAUX from backplane
  • Developed in alignment with the SOSA™ Technical Standard 1.0
  • RT3 backplane connectors for 100G support

Application Development

  • CoreFire Next Application Design Suite
    • Full Board Support Package for Fast and Easy Application Development
    • Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
    • Develop in GUI environment or create VHDL and use HDL environment
    • Built-in Debugger for Hardware in the loop Debugging
    • Supports High-Level Synthesis (HLS) Design Flow
  • VHDL BSP packages including full synthesis and simulation support
  • Communication Cores Included (10/40Gb Ethernet and AnnapMicro Protocol cores)
  • IOPE JTAG Access through RTM or Ethernet
  • Board control and status monitoring can be local and/or remote (via Ethernet)

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Technical Documents

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