WILDSTAR 2-Channel Direct RF 3U OpenVPX Module – WS3XV1+WHDMF1

The WILDSTAR™ 2-Channel Direct RF 3U OpenVPX Module is an assembled solution that is 100GbE-enabled, SOSA-aligned, and highly rugged and thermally-controlled. Directly digitize and process wideband signals with this high-performance 64.0/61.4 GSps Direct RF Module that includes Versal Premium processing.

Need the same SOSA-alignment and Versal processing and 100GbE capability in a 6U VPX form factor? See the WILDSTAR 6XV2 6U OpenVPX Board.

These FPGA modules are SOSA-aligned Plug-In Cards (PIC). They package the WS3XV1 Processor Baseboard and WHDMF1 ADC/DAC Mezzanine in one 3U VPX slot. High-performance digitizing and processing are powered by Versal™ Premium FPGA and a mezz-mounted 64.0/61.4 GSps Direct RF Transceiver.

VITA 66/67 optical/RF backplane support is included.

Review other OpenVPX 3U and Xilinx FPGA boards.

General Features

  • One Versal™ Premium VP1702 FPGA
    • Up to 10,896 DSP Slices and 5,557,720 logic cells
    • Up to 541 Mb of High Bandwidth, Low Latency UltraRAM
    • Five 32-bit LPDDR4 DRAM ports running up to 3732 MT/s
    • Dual-core 64-bit ARM Cortex-A72 running up to 1.4GHz
    • Dual-core 32-bit Cortex-R5F real-time processor running up to 450MHz
  • One Jariet Technologies Electra-MA Transceiver
    • Firmware and Software for four channel data transmit interface and clock trigger synchronization provided in CoreFire Next and VHDL source
  • Optional Front panel RS422/RS485 GPIO interface
  • Optional 2×40/100G Optical Transceivers to VITA 66 Backplane Interface
  • Multiple levels of hardware and software security

ADC Performance

  • Channels: 2
  • Sample Rate: 40 to 64.0 GSps
  • Resolution: 10 Bits in full-Nyquist
    • Spurs corrected to 12b resolution in full-Nyquist
  • Analog Input Bandwidth: 20GHz (-6dB) typical
  • Maximum Instantaneous Bandwidth: 6.4GHz
  • Run Time Selectable ADC Decimation: 8-1024x
    • 16b resolution for each I and Q decimated output
    • 12b mode is also available

DAC Performance

  • Channels: 2
  • Sample Rate: 40 to 61.4 GSps
  • Resolution: 10 Bits in full-Nyquist
  • Usable Analog Bandwidth: 36GHz
    • 15 GHz -3dB Bandwidth at 61.4 GSps
  • Maximum Instantaneous Bandwidth: 6.4GHz
  • Run Time Selectable DAC Interpolation: 8-1024x
    • 16b resolution for each I and Q interpolated input
    • 12b mode is also available

Backplane I/O

  • Eight 50Ω VITA 67 Connectors
    • Two Analog ADC Inputs
    • Two Analog DAC Outputs
    • One External Sample Clock Divided by 16 Input
    • One Optional External PLL Reference Input
    • Two Optional External Sample Clock Divide By 2 Inputs
  • Next Generation “WILD Mezzanine Card HSS” (WMC-H) Site
    • Optimized for JESD-based ADCs and DACs or Optical Transceivers
      • For High Bandwidth Applications
      • Annapolis Mezzanine products with “WH” prefix
    • SOSA-Aligned backplane I/O
    • Optimized for VITA 66/67 interfaces
    • Optimized for cooling
    • Allows larger form factor cards for higher IO density

Clock Synchronization

  • Software-selectable external clock input or onboard PLL clock
  • All ADCs and DACs across multiple mezzanine cards can be synchronized to the same sample using WILDSTAR Clock Distribution Boards

Mechanical and Environmental

  • 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.2 spacing
  • Supports OpenVPX payload profile:
    • SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n
    • SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-n (no P2A connectivity)
  • Available with 85°C ambient air temperature or card edge support and -55°C power-on
  • Available with -65°C to 105°C storage temperature
  • Air, Air-Flow-Through or Conduction Cooled
  • Only requires +12V and +3.3VAUX from backplane
  • Developed in alignment with the SOSA™ Technical Standard 1.0
  • RT3 backplane connectors for 100G support

Application Development

  • Full Board Support Package for fast and easy Application Development
  • Includes source for all provided software components and examples on Versal PEs
  • Open CoreFire™ Support
    • Graphical RTL generation of algorithm blocks
    • Feeds RTL development flow
  • Boot methodology and development flow path options:
    • Dynamic Function eXchange (DFX) via Abstract Shell Configuration
      • RTL design of the Reconfigurable Module (RM)
      • Design iteration speed up with reduced compile times
      • CIPS stands while RM region can be reloaded
    • Monolithic Configurations
      • Traditional full RTL design

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Technical Documents

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