WILD100 15-Slot 3U OpenVPX Backplane – W13C30

WILD100 15-Slot 3U OpenVPX Backplane (W13C30) is a 100Gb Ethernet-enabled 3U Backplane that incorporates slots for up to eight conduction-cooled 3U VPX Payload Boards, two 100GbE Switches, one SBC, one Radial Clock, and three VITA 62 power supplies.

It is VITA 65 compliant, SOSA-aligned, and designed and built in USA. Its sister Chassis is WC31F0.

The 15-Slot 3U OpenVPX Backplane incorporates slots for up to eight conduction-cooled 3U VPX Payload Boards, two 100GbE Switches, one SBC, one Radial Clock, and three VITA 62 power supplies (Standard or 12V-Heavy).

Also available is WABGM0 Chassis Manager.

See all of the Annapolis Chassis and Backplanes.

Chassis and Backplane

  • Fifteen 3U OpenVPX Slots
    • Eight 14.6.11 Primary RF/Compute Intensive profile
    • One 14.2.16 I/O Intensive SBC profile
    • Two 14.4.14/15 40/100GbE Switch profile
    • One 14.9.2 Timing profile
    • Three VITA 62 Power Supply Slots – Standard or 12V-Heavy
  • Input power is 28VDC per MIL-STD-704F
  • 25 Gbps Line Rates on Data and Expansion Planes
    • 25/40/100Gb Ethernet
    • SDR/DDR/QDR/EDR Infiniband
    • Gen 3/4 PCI Express
    • Custom protocols up to 25Gbps per lane
  • SOSA-aligned Backplane profiles
    • Payload Profile: SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n
    • Payload Profile: SLT3-PAY-1F1F2U1TU1T1U1T-14.2.16
    • Switch Profile: SLT3-SWH-6F1U7U-14.4.14/15
    • Timing Profile: SLT3x-TIM-2S1U22S1U2U1H-14.9.2
  • VITA 66.5C and VITA 67.3C for payload slots
  • Integrated ultra-low skew AUXCLK/REFCLK radial distribution
  • WABGM0 Chassis manager connector handles JTAG, maintenance ports (UARTs) and control
  • Support for CLK1 direct connection between payload slots (2,3,5,6,8,9,11,12) to Chassis Manager FPGA
  • I/O Intensive Slot 1 backplane I/O
    • GPIO connector for XMC IO, SER01, GPIO and USB 2.0
    • USB 3.0 and Display Port Connectors (not available with all temperature options)
  • Rear connectors for chassis manager, per slot JTAG, Maintenance Ports (UARTs) and control
    • Allows for optional backplane accessory interfaces without additional cabling such as WABGM0 Chassis Manager

Optional WABGM0 Chassis Manager

  • SOSA-aligned and VITA 46.11 compliant
  • Front pluggable in SBC Slot 1 or plugged directly onto backplane
  • Xilinx UltraScale+ ZU5EG MPSoC running Linux for CHmC
    • Processing Subsystem (PS)
      • Quad core A53 ARM running at 1.2 GHz
      • Dual core R5 ARM
      • 4GB DDR4 DRAM
      • 128MB QSPI NOR
    • Programmable Logic subsystem (PL)
      • 256K System Logic cells in Programmable Logic
      • 18Mb of UltraRAM
      • 128MB QSPI NOR
      • Dual 128KB battery backed NV SRAM
  • Integrated JTAG access/control from chassis manager to each slot
    • External JTAG connection with SW selectable multiplexing from each slot
    • Xilinx JTAG over ethernet via Chassis Manager
  • Optional MIL-STD-1553 support
  • Optional advanced security features

Mechanical and Environmental

  • Temperature
    • Operating: -40 to +85°C
    • Storage: -55 to +105°C
  • Humidity
    • Operating and Storage: 5 to 95% Noncondensing
  • Shock: 40G per VITA 47 Class OS2
  • Vibration per VITA 47 Class V3
    • 5 Hz to 100 Hz PSD increasing at 3 dB/octave
    • 100 Hz to 1000 Hz PSD = 0.1 g2/Hz
    • 1000 Hz to 2000 Hz PSD decreasing at 6 dB/octave

The following documentation is available for registered users of our site. Please log in or feel free to register for our site.

Technical Documents

For additional documentation, please contact your Sales Representative.

Product Images