Open Project Builder
The Annapolis Micro Systems Open Project Builder™ provides the efficiency of CoreFire Next™ development with the flexibility of HDL. It integrates the CoreFire environment with Annapolis HDL board support packages.
Open Project Builder is compatible with Arria 10, UltraScale/UltraScale+, and Stratix 10 boards.

Open Project Builder™ users have the capability to use FPGA IP from multiple sources, such as CoreFire Next, High-Level Synthesis (HLS), other HDL, etc. Open Project Builder can also port IP to/from other hardware platforms. It uses standard Avalon and AXI IP interfaces. Open Project Builder provides fast portability of applications between Intel and Xilinx and to newer FPGA families.
Features
- Board Support Packages for Arria 10 and UltraScale WILDSTAR Boards
- Works from High Level, Data Flow Concept of the Application
- Intelligent Board Support Generation Wizard for HDL Users
- Combines GUI Design Entry and Debug Tools with Tested, Optimized Open Project Builder™ IP Cores
- Drag and Drop High and Low Level Modules
- Open Project Builder Modules Incorporate Years of Application Development Experience
- Open Project Builder Tools and Modules are Intelligent
- Modules Automatically Handle Synchronization
- Manage Clocks and Other Low Level Hardware Signals
- Guarantee Correct Control by Design Modules “Know How” to Interact With Each Other
- Board Support Packages Incorporate Hardware Details of the Boards – Invisible to Users
- Supports Multiple Data Types – Bit, Signed and Unsigned Integers Single Precision Floating Point, Integer and Floating Point Complex Data Types and Array Types.
- Integrates with Matlab™ Simulation Flow
Benefits
- Provides the efficiency of Open Project Builder Development with the Flexibility of HDL
- Extremely Efficient FPGA application development using Annapolis Board Support Packages
- Ability to port IP to/from other platforms
- Standard Avalon and AXI IP interfaces
- Fast Portability of Application between Intel and Xilinx and to newer FPGA families
- Ability to use FPGA IP from other sources (Corefire Next, High-Level Synthesis, other HDL, etc)